US4924339A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input protecting circuit in use with a MOS semiconductor device
Assignee: Toshiba Corp
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Filing: 1988-12-28
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Granted: 1990-05-08
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Expires: 2008-12-28
Abstract
Abstract A bipolar transistor for clamping an excess input potential is provided near an input pad. A signal from the input pad is supplied through a wire to the gate of a MOS transistor in the input stage. A diode is provided near the gate of the MOS transistor. The diode absorbs a potential oscillation generated in the wire near the gate of the transistor, which is due to action of an inductance involved in the wire.
Inventors
- 👤 Shigeru Atsumi
- 👤 Toru Yoshida
- 👤 Yasuo Kawahara
- 👤 Fuminari Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:51
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D89/611; H10D89/711; H10D89/931
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
128 words
An input protecting circuit in use with a MOS semiconductor device having an input stage, comprising: an input pad; a MOS transistor in the input stage of the MOS semiconductor device, the gate of which receives a signal from said input pad; a wire interconnecting said input pad and the gate of said MOS transistor in said input stage; a first protecting element provided near said input pad and connected at one end to said interconnecting wire; and a second protecting element provided near the gate of said MOS transistor and connected at one end to said interconnecting wire, said second protecting element being formed in a circuit block which is enclosed by a guard ring region and contains said MOS transistor of the input stage formed therein.
Claim 2
Dependent Claim
128 words
An input protecting circuit in use with a MOS semiconductor device having an input stage, comprising: an input pad; a MOS transistor in the input stage of the MOS semiconductor device, the gate of which receives a signal from said input pad; a wire interconnecting said input pad and the gate of said MOS transistor in said input stage; a first protecting element provided near said input pad and connected at one end to said interconnecting wire; and a second protecting element provided near the gate of said MOS transistor and connected at one end to said interconnecting wire, said second protecting element being formed in a circuit block which is enclosed by a guard ring region and contains said MOS transistor of the input stage formed therein.
Claim 3
Dependent Claim
18 words
An input protecting circuit according to claim 1, wherein a resistor is inserted in series in said wire.
Claim 4
Dependent Claim
17 words
An input protecting circuit according to claim 1, wherein said first protecting element is one bipolar transistor.
Claim 5
Dependent Claim
18 words
An input protecting circuit according to claim 1, wherein said first protecting element includes a pair of diodes.
Claim 6
Dependent Claim
19 words
An input protecting circuit according to claim 1, wherein said first protecting element includes a pair of bipolar transistors.
Claim 7
Dependent Claim
16 words
An input protecting circuit according to claim 1, wherein said second protecting element includes a diode.
Claim 8
Dependent Claim
27 words
An input protecting circuit according to claim 1, wherein said second protecting element includes a second MOS transistor having a source and drain connected to said wire.
Claim 9
Dependent Claim
18 words
An input protecting circuit according to claim 7, wherein a gate of said second MOS transistor is grounded.
Claim 10
Dependent Claim
23 words
An input protecting circuit according to claim 7, wherein a gate of said second MOS transistor is connected to a power source potential.
Claim 11
Dependent Claim
180 words
An input protecting circuit in use with a MOS semiconductor device, having an input stage, comprising: an input pad; a MOS transistor in the input stage of the MOS semiconductor device, a gate of which receives a signal from said input pad; a wire interconnecting said input pad and the gate of said MOS transistor in said input stage; a first protecting element provided near said input pad and connected at one end to said interconnecting wire, said first protecting element releasing most of certain energy applied to said input pad due to high voltage noise down to a reference potential level; and a second protecting element provided near the gate of said MOS transistor and connected at one end to said interconnecting wire, said second protecting element being formed in a circuit block which is enclosed by a guard ring region and contains said MOS transistor of the input stage formed therein, said second protecting element releasing a very small amount of energy applied to said input pad due to high voltage noise down to a reference potential level.
Claim 12
Dependent Claim
180 words
An input protecting circuit in use with a MOS semiconductor device, having an input stage, comprising: an input pad; a MOS transistor in the input stage of the MOS semiconductor device, a gate of which receives a signal from said input pad; a wire interconnecting said input pad and the gate of said MOS transistor in said input stage; a first protecting element provided near said input pad and connected at one end to said interconnecting wire, said first protecting element releasing most of certain energy applied to said input pad due to high voltage noise down to a reference potential level; and a second protecting element provided near the gate of said MOS transistor and connected at one end to said interconnecting wire, said second protecting element being formed in a circuit block which is enclosed by a guard ring region and contains said MOS transistor of the input stage formed therein, said second protecting element releasing a very small amount of energy applied to said input pad due to high voltage noise down to a reference potential level.
Claim 13
Dependent Claim
17 words
An input protecting circuit according to claim 10, wherein said first protecting element includes a bipolar transistor.
Claim 14
Dependent Claim
18 words
An input protecting circuit according to claim 10, wherein said first protecting element includes a pair of diodes.
Claim 15
Dependent Claim
19 words
An input protecting circuit according to claim 10, wherein said first protecting element includes a pair of bipolar transistors.
Claim 16
Dependent Claim
16 words
An input protecting circuit according to claim 10, wherein said second protecting element includes a diode.
Claim 17
Dependent Claim
28 words
An input protecting circuit according to claim 10, wherein said second protecting element includes a second MOS transistor having a source and a drain connected to said wire.
Claim 18
Dependent Claim
19 words
An input protecting circuit according to claim 15, wherein said second MOS transistor has a gate which is grounded.
Claim 19
Dependent Claim
24 words
An input protecting circuit according to claim 15, wherein said second MOS transistor has a gate which is connected to a power source potential.
Claim 20
Dependent Claim
19 words
An input protecting circuit according to claim 10, further including a resistor is inserted in series in said wire.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-07 | 1993-11-06 | 1994-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-07 | 1997-11-06 | 1998-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-07 | 2001-11-06 | 2002-05-08 | $7700.00 | Window Closed / Lapsed |