US5099302A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrable active diode
Assignee: STMicroelectronics SA
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Filing: 1990-12-20
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Granted: 1992-03-24
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Expires: 2010-12-20
Abstract
Abstract An active diode for protecting from reverse voltages a monolithic structure comprising a logic portion and a power portion of the vertical MOS transistor type. The logic portion is constituted by conventional MOS transistors (TL-1) placed in a well (b 64) of a first conductivity type formed in a substrate (60) of the second conductivity type, the rear surface (74) of the substrate corresponding to the drain of the vertical MOS transistor. The active diode comprises a MOS transistor (TS), the gate of which (65) is controlled by a voltage whose sign is representative of the supply voltage polarity, the drain region of which (67) is grounded, and a highly doped deep area (71) of the first conductivity type extending from the upper surface (69) of the well (64), said area being connected to the source (66) of the MOS transistor.
Inventors
- 👤 Antoine Pavlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:58
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/101; H10D84/141; H10D62/00; H10D62/10; H10D62/13; H10D62/141; H10D62/142; H10D12/00; H10D12/411; H10D64/00; H10D64/60; H10D64/64; H10D64/647; H10D84/148; H10D89/00; H10D89/60; H10D89/601; H10D89/611
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
294 words
A semiconductor device having reverse power supply polarity protection, comprising: a semiconductor substrate of a first conductivity type having a lower layer having a high impurity concentration and an upper layer on said lower layer, said upper layer having an impurity concentration lower than said high impurity concentration of said lower layer; a well region of a second conductivity type opposite said first conductivity type and of a first impurity concentration, said well region formed in said upper layer of said semiconductor substrate and having a predetermined depth; a vertical first MOS transistor formed in said semiconductor substrate outside said well region, said vertical MOs transistor including source and drain regions of said first conductivity type formed respectively in said upper and lower layers of said substrate, said source and drain receiving an operating voltage therebetween having a particular polarity; a highly doped region of said second conductivity type having a greater impurity concentration than said impurity concentration of said well region, said highly doped region formed in said well region and having no greater than said predetermined depth therein; a second MOS transistor formed in said well region, said second MOS transistor having first and second spaced apart source/drain regions of said first conductivity type formed in said well region, a channel region located between said source/drain regions, a gate oxide region formed on said upper layer of said semiconductor substrate above said channel region and a gate electrode formed on said gate oxide region, said first source/drain region formed adjacent and electrically connected to said highly doped region, said second source/drain region connected to ground; and means for applying, to said gate electrode of said second MOS transistor, a voltage having a polarity corresponding to said particular polarity of said operating voltage.
Claim 2
Dependent Claim
294 words
A semiconductor device having reverse power supply polarity protection, comprising: a semiconductor substrate of a first conductivity type having a lower layer having a high impurity concentration and an upper layer on said lower layer, said upper layer having an impurity concentration lower than said high impurity concentration of said lower layer; a well region of a second conductivity type opposite said first conductivity type and of a first impurity concentration, said well region formed in said upper layer of said semiconductor substrate and having a predetermined depth; a vertical first MOS transistor formed in said semiconductor substrate outside said well region, said vertical MOs transistor including source and drain regions of said first conductivity type formed respectively in said upper and lower layers of said substrate, said source and drain receiving an operating voltage therebetween having a particular polarity; a highly doped region of said second conductivity type having a greater impurity concentration than said impurity concentration of said well region, said highly doped region formed in said well region and having no greater than said predetermined depth therein; a second MOS transistor formed in said well region, said second MOS transistor having first and second spaced apart source/drain regions of said first conductivity type formed in said well region, a channel region located between said source/drain regions, a gate oxide region formed on said upper layer of said semiconductor substrate above said channel region and a gate electrode formed on said gate oxide region, said first source/drain region formed adjacent and electrically connected to said highly doped region, said second source/drain region connected to ground; and means for applying, to said gate electrode of said second MOS transistor, a voltage having a polarity corresponding to said particular polarity of said operating voltage.
Claim 3
Dependent Claim
38 words
A semiconductor device according to claim 1, wherein said gate electrode of said second MOS transistor is connected to a resistor and a diode together connected in parallel for supplying a control signal to said second MOS transistor.
Claim 4
Dependent Claim
27 words
A semiconductor device according to claim 1, further comprising a zener diode connected between said gate electrode and said second source/drain region of said second MOS transistor.
Claim 5
Dependent Claim
39 words
The semiconductor device of claim 1 further comprising a metal layer formed on said upper layer of said semiconductor substrate, said metal layer electrically connecting said first source/drain region of said second MOS transistor to said highly doped region.
Claim 6
Dependent Claim
20 words
The semiconductor device of claim 1 wherein said highly doped region extends throughout said predetermined depth of said well region.
Claim 7
Dependent Claim
296 words
A semiconductor device having reverse power supply polarity protection, comprising: a semiconductor substrate of a first conductivity type having upper and lower main surfaces; an overdoped layer of said first conductivity type and having an impurity concentration greater than an impurity concentration of said semiconductor substrate, said overdoped layer formed on the lowe main surface of said semiconductor substrate; a well region of a second conductivity type opposite said first conductivity type formed in said semiconductor substrate and having a predetermined depth; a vertical first MOS transistor formed outside said well region, said first vertical MOS transistor including a source region formed in said semiconductor substrate and a drain region formed in said overdoped layer, said source and drain regions receiving an operating voltage therebetween having a particular polarity; a highly doped region of said second conductivity type having a greater impurity concentration than an impurity concentration of said well region, said highly doped region formed in said well region and having no greater than said predetermined depth; a second MOS transistor formed in said well region, said second MOS transistor having first and second spaced apart source/drain regions of said first conductivity type and of a higher impurity concentration than said semiconductor substrate impurity concentration, said source/drain regions formed in said semiconductor substrate, a channel region located between said source/drain regions, a gate oxide layer formed on said main surface of said semiconductor substrate above said channel region and gate electrode formed on said gate oxide region, said first source/drain region formed adjacent and electrically connected to said highly doped region, said second source/drain region connected to ground; and means for applying, to said gate electrode of said second MOS transistor, a voltage having a polarity corresponding to said particular polarity of said operating voltage.
Claim 8
Dependent Claim
296 words
A semiconductor device having reverse power supply polarity protection, comprising: a semiconductor substrate of a first conductivity type having upper and lower main surfaces; an overdoped layer of said first conductivity type and having an impurity concentration greater than an impurity concentration of said semiconductor substrate, said overdoped layer formed on the lowe main surface of said semiconductor substrate; a well region of a second conductivity type opposite said first conductivity type formed in said semiconductor substrate and having a predetermined depth; a vertical first MOS transistor formed outside said well region, said first vertical MOS transistor including a source region formed in said semiconductor substrate and a drain region formed in said overdoped layer, said source and drain regions receiving an operating voltage therebetween having a particular polarity; a highly doped region of said second conductivity type having a greater impurity concentration than an impurity concentration of said well region, said highly doped region formed in said well region and having no greater than said predetermined depth; a second MOS transistor formed in said well region, said second MOS transistor having first and second spaced apart source/drain regions of said first conductivity type and of a higher impurity concentration than said semiconductor substrate impurity concentration, said source/drain regions formed in said semiconductor substrate, a channel region located between said source/drain regions, a gate oxide layer formed on said main surface of said semiconductor substrate above said channel region and gate electrode formed on said gate oxide region, said first source/drain region formed adjacent and electrically connected to said highly doped region, said second source/drain region connected to ground; and means for applying, to said gate electrode of said second MOS transistor, a voltage having a polarity corresponding to said particular polarity of said operating voltage.
Claim 9
Dependent Claim
38 words
A semiconductor device according to claim 6 wherein said gate electrode of said second MOS transistor is connected to a resistor and a diode together connected in parallel for supplying a control signal to said second MOs transistor.
Claim 10
Dependent Claim
27 words
A semiconductor device according to claim 6, further comprising a zener diode connected between said gate electrode and said second source/drain region of said second MOS transistor.
Claim 11
Dependent Claim
40 words
The semiconductor device of claim 6 further comprising a metal layer formed on said upper main surface of said semiconductor substrate, said metal layer electrically connecting said first source/drain region of said second MOS transistor to said highly doped region.
Claim 12
Dependent Claim
20 words
The semiconductor device of claim 6 wherein said highly doped region extends throughout said predetermined depth of said well region.
Claim 13
Dependent Claim
24 words
The semiconductor device of claim 6 further comprising a metalization layer formed on a main surface of said overdoped layer opposite said semiconductor substrate.
Claim 14
Dependent Claim
307 words
A semiconductor device having reverse power supply polarity protection, comprising: a semiconductor substrate of a first conductivity type having upper and lower main surfaces; an overdoped layer of said first conductivity type and having an impurity concentration greater than an impurity concentration of said semiconductor substrate, said overdoped layer formed on the lower main surface of said semiconductor substrate; a metalization layer formed on a main surface of said overdoped layer opposite said semiconductor substrate; a well region of a second conductivity type opposite said first conductivity type formed in said semiconductor substrate and having a predetermined depth; a vertical first MOS transistor formed in said semiconductor substrate and in said overdoped layer outside said well region, said vertical MOS transistor including a source region formed in said semiconductor substrate and a drain region formed in said overdoped layer, said source and drain regions receiving an operating voltage therebetween having a particular polarity; a highly doped region of said second conductivity type having a greater impurity concentration than an impurity concentration of said well region, said highly doped region formed in said well region and having no greater than said predetermined depth; and a second MOPS transistor formed in said well region, said second MOS transistor having first and second spaced apart source/drain regions of said first conductivity type formed in said well region, a channel region formed between said source/drain regions, a gate oxide layer formed on said main surface of said semiconductor substrate above said channel region and a gate electrode formed on said gate oxide region, said first source/drain region formed adjacent and electrically connected to said highly doped region, said second source/drain region connected to ground; and means for applying, to said gate electrode of said second MOS transistor, a voltage having a polarity corresponding to said particular polarity of said operating voltage.
Claim 15
Dependent Claim
307 words
A semiconductor device having reverse power supply polarity protection, comprising: a semiconductor substrate of a first conductivity type having upper and lower main surfaces; an overdoped layer of said first conductivity type and having an impurity concentration greater than an impurity concentration of said semiconductor substrate, said overdoped layer formed on the lower main surface of said semiconductor substrate; a metalization layer formed on a main surface of said overdoped layer opposite said semiconductor substrate; a well region of a second conductivity type opposite said first conductivity type formed in said semiconductor substrate and having a predetermined depth; a vertical first MOS transistor formed in said semiconductor substrate and in said overdoped layer outside said well region, said vertical MOS transistor including a source region formed in said semiconductor substrate and a drain region formed in said overdoped layer, said source and drain regions receiving an operating voltage therebetween having a particular polarity; a highly doped region of said second conductivity type having a greater impurity concentration than an impurity concentration of said well region, said highly doped region formed in said well region and having no greater than said predetermined depth; and a second MOPS transistor formed in said well region, said second MOS transistor having first and second spaced apart source/drain regions of said first conductivity type formed in said well region, a channel region formed between said source/drain regions, a gate oxide layer formed on said main surface of said semiconductor substrate above said channel region and a gate electrode formed on said gate oxide region, said first source/drain region formed adjacent and electrically connected to said highly doped region, said second source/drain region connected to ground; and means for applying, to said gate electrode of said second MOS transistor, a voltage having a polarity corresponding to said particular polarity of said operating voltage.
Claim 16
Dependent Claim
38 words
A semiconductor device according to claim 12 wherein said gate electrode of said second MOS transistor is connected to a resistor and a diode together connected in parallel for supplying a control signal to said second MOS transistor.
Claim 17
Dependent Claim
27 words
A semiconductor device according to claim 12, further comprising a zener diode connected between said gate electrode and said second source/drain region of said second MOS transistor.
Claim 18
Dependent Claim
48 words
The semiconductor device of claim 12 further comprising a metal layer formed on said upper main surface of said semiconductor substrate, said metal layer electrically connecting said second source/drain region of said second MOS transistor to said highly doped region at said upper surface of said semiconductor substrate.
Claim 19
Dependent Claim
20 words
The semiconductor device of claim 12 wherein said highly doped region extends throughout said predetermined depth of said well region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-24 | 1995-09-23 | 1996-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-24 | 1999-09-23 | 2000-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-24 | 2003-09-23 | 2004-03-24 | $7700.00 | Window Closed / Lapsed |