Patent US5225774A successfully refreshed from Google Patents.
US5225774A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Renesas Electronics Corp
•
Filing: 1991-07-16
•
Granted: 1993-07-06
•
Expires: 2011-07-16
Abstract
Abstract A semiconductor integrated circuit includes transfer gates to separate a plurality of functional devices and an input or output buffer circuit, and a test circuit to connect the input buffer circuit and the output buffer circuit directly, when input, output, and input and output characteristics of the input buffer circuit and the output buffer circuit are tested. Therefore, only one test pattern is used, so that the characteristics of the buffer circuits are tested easily in a short time and exactly.
Inventors
- 👤 Hirohisa Imamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:39
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318505; G01R31/2851; G01R31/2884; G01R31/31712; G01R31/31715
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
205 words
A semiconductor integrated circuit comprising: a plurality of functional devices connected to each other to carry out a predetermined operation; an input buffer circuit connected to input terminals to supply input signals therefrom to said functional devices; an output buffer circuit connected to output terminals to supply output signals from said functional devices to said output terminals; first means for separating connections of said functional devices when a characteristic test of said input and output buffer circuits is carried out; second means for separating a connection selected from a first connection between said input buffer circuit and said functional devices and a second connection between said functional devices and said output buffer circuit when said characteristic test is carried out; and means for connecting said input and output buffer circuits when said second means separates said connection, said connecting means connecting said input and output terminals via said input and output buffer circuits when said characteristic test is carried out, and including a logic circuit operating to provide signal paths via said input and output buffer circuits from said input terminals to corresponding terminals of said output terminals so that characteristics of both said input and output buffer circuits are detected through said signal paths.
Claim 2
Dependent Claim
205 words
A semiconductor integrated circuit comprising: a plurality of functional devices connected to each other to carry out a predetermined operation; an input buffer circuit connected to input terminals to supply input signals therefrom to said functional devices; an output buffer circuit connected to output terminals to supply output signals from said functional devices to said output terminals; first means for separating connections of said functional devices when a characteristic test of said input and output buffer circuits is carried out; second means for separating a connection selected from a first connection between said input buffer circuit and said functional devices and a second connection between said functional devices and said output buffer circuit when said characteristic test is carried out; and means for connecting said input and output buffer circuits when said second means separates said connection, said connecting means connecting said input and output terminals via said input and output buffer circuits when said characteristic test is carried out, and including a logic circuit operating to provide signal paths via said input and output buffer circuits from said input terminals to corresponding terminals of said output terminals so that characteristics of both said input and output buffer circuits are detected through said signal paths.
Claim 3
Dependent Claim
184 words
A semiconductor integrated circuit comprising; a plurality of input terminals each applied with input signals; a plurality of output terminals each providing output signals; a plurality of functional devices having predetermined functions, respectively; an input buffer circuit connected between said input terminals and said plurality of functional devices; an output buffer circuit connected between said plurality of functional devices and said output terminals; means for separating said functional devices and said output buffer circuit when characteristics of said input buffer circuit and said output buffer circuit are tested; and means for connecting said input buffer circuit and said output buffer circuit when said characteristics of said input buffer circuit and said output buffer circuit are tested, said connecting means connecting said input and output terminals via said input and output buffer circuits when said characteristic test is carried out, and including a logic circuit operating to provide signal paths vis said input and output buffer circuits from said input terminals to corresponding terminals of said output terminals so that characteristics of both said input and output buffer circuits are detected through said signal paths.
Claim 4
Dependent Claim
184 words
A semiconductor integrated circuit comprising; a plurality of input terminals each applied with input signals; a plurality of output terminals each providing output signals; a plurality of functional devices having predetermined functions, respectively; an input buffer circuit connected between said input terminals and said plurality of functional devices; an output buffer circuit connected between said plurality of functional devices and said output terminals; means for separating said functional devices and said output buffer circuit when characteristics of said input buffer circuit and said output buffer circuit are tested; and means for connecting said input buffer circuit and said output buffer circuit when said characteristics of said input buffer circuit and said output buffer circuit are tested, said connecting means connecting said input and output terminals via said input and output buffer circuits when said characteristic test is carried out, and including a logic circuit operating to provide signal paths vis said input and output buffer circuits from said input terminals to corresponding terminals of said output terminals so that characteristics of both said input and output buffer circuits are detected through said signal paths.
Claim 5
Dependent Claim
58 words
A semiconductor integrated circuit, according to claim 2, wherein: said separating means comprises a first gate set which is connected between said functional devices and said output terminals, and becomes ON state when said semiconductor integrated circuit normally operates and becomes OFF state, when said characteristics of said input buffer circuit and said output buffer circuit are tested.
Claim 6
Dependent Claim
61 words
A semiconductor integrated circuit, according to claim 3, wherein: said connecting means further comprises a second gate set which is connected between said input buffer circuit and said output buffer circuit, and becomes OFF state, when said semiconductor integrated circuit normally operates, and becomes ON state, when said characteristics of said input buffer circuit and said output buffer circuit are tested.
Claim 7
Dependent Claim
53 words
A semiconductor integrated circuit, according to claim 4, wherein: said input terminals comprise a test signal terminal applied with test signals to change said first gate set to OFF state and said second gate set to ON state, when said characteristics of said input buffer circuit and said output buffer circuit are tested.
Claim 8
Dependent Claim
16 words
A semiconductor integrated circuit according to claim 1, wherein said logic circuit is an inverter circuit.
Claim 9
Dependent Claim
15 words
A semiconductor integrated circuit according to claim 2, wherein said logic circuit includes an inverter.
References Cited (Backward Citations)
US4357703A
Cited
US4527115A
Cited
US4864165A
Cited
US4698588A
Cited
US4931722A
Cited
US4780666A
Cited
US4864579A
Cited
US4870345A
Cited
US4782283A
Cited
US4912395A
Cited
US5012185A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-05 | 1997-01-04 | 1997-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-05 | 2001-01-04 | 2001-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-05 | 2005-01-04 | 2005-07-06 | $7700.00 | Window Closed / Lapsed |