US5225368A
Expired / Lapsed
US
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Method of producing strained-layer semiconductor devices via subsurface-patterning
Assignee: United States Department of Energy
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Filing: 1991-02-08
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Granted: 1993-07-06
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Expires: 2011-02-08
Abstract
Abstract A method is described for patterning subsurface features in a semiconductor device, wherein the semiconductor device includes an internal strained layer. The method comprises creating a pattern of semiconductor material over the semiconductor device, the semiconductor material having a predetermined thickness which stabilizes areas of the strained semiconductor layer that lie beneath the pattern. Subsequently, a heating step is applied to the semiconductor device to cause a relaxation in areas of the strained layer which do not lie beneath the semiconductor material pattern, whereby dislocations result in the relaxed areas and impair electrical transport therethrough.
Inventors
- 👤 Brian W. Dodson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 01:36
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/015; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2907; H10P14/2911; H10P14/32; H10P14/3202; H10P14/3214; H10P14/3218; H10P14/3221; H10P14/3242; H10P14/3244; H10P14/3251; H10P14/34; H10P14/3402; H10P14/3414; H10P14/3421; H10P95/00; H10P95/90; H10P95/904; Y; Y10; Y10S; Y10S438/00; Y10S438/938
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
110 words
A method for patterning subsurface dislocation features in a semiconductor device, wherein said semiconductor device includes a semiconductor substrate and a strained semiconductor layer, the method comprising: (a) creating a pattern of semiconductor material on said semiconductor device, said deposited material is of a thickness which thermodynamically stabilizes areas of said strained semiconductor layer that lie beneath said pattern; and (b) generating a plurality of dislocations in select areas of said strained semiconductor layer by applying heat to said semiconductor device to cause a relaxation in areas of said strained layer which do not lie beneath said semiconductor material pattern, thereby creating said plurality of dislocations in said relaxed areas.
Claim 2
Independent Claim
110 words
A method for patterning subsurface dislocation features in a semiconductor device, wherein said semiconductor device includes a semiconductor substrate and a strained semiconductor layer, the method comprising: (a) creating a pattern of semiconductor material on said semiconductor device, said deposited material is of a thickness which thermodynamically stabilizes areas of said strained semiconductor layer that lie beneath said pattern; and (b) generating a plurality of dislocations in select areas of said strained semiconductor layer by applying heat to said semiconductor device to cause a relaxation in areas of said strained layer which do not lie beneath said semiconductor material pattern, thereby creating said plurality of dislocations in said relaxed areas.
Claim 3
Dependent Claim
61 words
The method as recited in claim 1 wherein said semiconductor device includes a planar, stop-etch layer, and said pattern of semiconductor material is created thereon, the method further comprising: (c) removing said pattern of semiconductor material with an etchant which does not etch said stop-etch layer, to restore a planar surface for said semiconductor device subsequent to heating said semiconductor material.
Claim 4
Dependent Claim
66 words
The method as recited in claim 1 wherein said strained semiconductor layer has a thickness h and the thickness of semiconductor material thereover, including said patterned semiconductor material is H, and wherein the value of h can be determined from: h.sub.c <h<h.sub.c.sup.* where ##EQU3## h.sub.c.sup.* =ah.sub.c -H ##EQU4## where Ln represents the natural log function, and E is the strain exhibited in said strained semiconductor layer.
Claim 5
Dependent Claim
54 words
The method as recited in claim 1 wherein said semiconductor device has a set of one or more source and drain regions formed in said substrate and in a plurality of epitaxial layers overlying said substrate and where step (b) accomplishes an annealing of said regions at the same time said dislocations are created.
Claim 6
Dependent Claim
28 words
The method as recited in claim 1 wherein said strained semiconductor layer is an active layer in said device and said dislocations create regions of impaired electrical transport.
Claim 7
Dependent Claim
27 words
The method as recited in claim 1 wherein said dislocations act as centers for recombination of photoexcited carriers when said semiconductor device is employed for photodetection purposes.
References Cited (Backward Citations)
US4571486A
Cited
US4605447A
Cited
US4585491A
Cited
US4727555A
Cited
US4654090A
Cited
US4806996A
Cited
US4751194A
Cited
US4771010A
Cited
US4876210A
Cited
US4835116A
Cited
EP0319207A2
Cited
US4927471A
Cited
US4876219A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-05 | 1997-01-04 | 1997-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-05 | 2001-01-04 | 2001-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-05 | 2005-01-04 | 2005-07-06 | $7700.00 | Window Closed / Lapsed |