RISC system performing calls and returns without saving or restoring window pointers and delaying saving until multi-register areas are filled

Claim 2

A processor system, comprising: a main storage for storing data and instructions, some of said instructions having an operation code and an operand part including a register designating part, and wherein said instructions form a plurality of programs, at least one of which contains a plurality of subprograms; first means for decoding instructions of said program; a plurality of first registers which are allocated to said program, one first group of said first registers being employed in the execution of said plurality of programs, and at least one second group of said first registers forming a plurality of multi-register areas, each of which is selectively allocated to said subprograms; a second register storing information which identifies one of said multi-register areas allocated to one of said subprograms and the content of which is controlled by the operation code of instructions decoded by said first means, wherein one of the registers in said multi-register area identified by said second register is specified by said register designating part of an instruction; and processing means for processing instructions according to decoded operation codes and the content of registers in the multi-register area identified by said second register and specified by decoded register designating parts, wherein the operation codes of some instructions indicate that the content of said second register is advanced or retracted and the operation codes of other instructions indicate that a subprogram to be allocated to a multi-register area is to be called from a current subprogram without advancement of the contents of said second register or that the current subprogram is to be returned to a previous subprogram without retraction of the contents of said second register.

Claim 3

A processor system according to claim 1, wherein said first registers in said second group are addressable registers disposed in sequence in a ring-bank configuration.

Claim 4

A processor system according to claim 1, wherein said first means for decoding instructions, said plurality of first registers and said processing means are fabricated on a single semiconductor chip as a microprocessor.

Claim 5

A processor system, comprising: a main storage for storing instructions having an operation code and an operand part, the operand part of at least some of said instructions including a register designating part, a group of said instructions forming a program which contains a plurality of subprograms; a plurality of first registers forming a plurality of multi-register areas each of which is selectively allocated to said subprograms; first means for decoding instructions, said instructions including first instructions having operation codes which indicate that a subprogram is to be called from a current subprogram or that the current subprogram is to be returned to the previous subprogram and second instructions which specify to change an indication of a multi-register area; second means controlled only by second instructions for indicating a multi-register area of first registers allocated to at least one current subprogram, wherein at least some of said subprograms do not include a second instruction, whereby a single multi-register area is employed in the execution of plural subprograms; processing means for processing instructions in response to the operation code thereof as decoded by said first means, including means for effecting operations using the content of a register in a multi-register area indicated by said second means and specified by a register designating part of an instructions.

Claim 6

A processor system, comprising: a main storage for storing instructions having an operation code and an operand part, the operand part of at least some of said instructions including a register designating part, a group of said instructions forming a program which contains a plurality of subprograms; a plurality of first registers forming a plurality of multi-register areas each of which is selectively allocated to said subprograms; first means for decoding instructions, said instructions including first instructions having operation codes which indicate that a subprogram is to be called from a current subprogram or that the current subprogram is to be returned to the previous subprogram and second instructions which specify to change an indication of a multi-register area; second means controlled only by second instructions for indicating a multi-register area of first registers allocated to at least one current subprogram, wherein at least some of said subprograms do not include a second instruction, whereby a single multi-register area is employed in the execution of plural subprograms; processing means for processing instructions in response to the operation code thereof as decoded by said first means, including means for effecting operations using the content of a register in a multi-register area indicated by said second means and specified by a register designating part of an instructions.

Claim 7

A processor system according to claim 4, wherein said second means including a second register whose content designates a multi-register area of first registers, said processor means further including means responsive to execution of a second instruction for altering the content of said second register to advance or retract the indication of a multi-register area forming said content.

Claim 8

A processor system according to claim 4, wherein said first registers are addressable registers disposed in sequence in a ring-bank configuration.

Claim 9

A processor system according to claim 4, wherein said first means for decoding instructions, said plurality of first registers and said processing means are fabricated on a single semiconductor chip as a microprocessor.

Claim 10

A processor system, comprising: a main storage for storing data and instructions, at least some instructions having an operation code and an operand part including a register designating part, and wherein said instructions are part of a program which contains a plurality of subprograms, and further including a save area for the operations of saving data therein or restoring data therefrom; first means for decoding instructions of said program; a plurality of first registers which are allocated to said program, and at least some of first registers forming a plurality of multi-register areas each of which is selectively allocated to said subprograms; a second register storing information which identifies one of said multi-register areas allocated to one of said subprograms and the content of which is controlled by the operation code of instructions decoded by said first means, wherein one of the registers in said multi-register area identified by said second register is specified by said register designating part; a third register for indicating a position of one of said multi-register areas of said first registers for triggering said data saving or restoring operations, wherein the operation codes of some instructions indicate operations in which the content of said second register is advanced or retracted, or a subprogram is called from a current subprogram or the current subprogram is returned to a previous subprogram; and processing means for processing instructions according to decoded operation codes and contents of registers indicated by said second register and specified by decoded register designating parts, including means responsive to all of said multi-register areas being occupied by subprograms, as indicated by a determination of correspondence between the contents of said second and third registers as a result of said advancing or calling operations, for saving the content of the multi-register area specified by the content of said third register to said save area of said main storage, and for advancing the content of the third register corresponding to the advance of the content of said second register, and means responsive to determination of correspondence between the contents of said second and third registers as a result of said retracting or returning operations for restoring data from said save area of said main storage to the multi-register area specified by the content of said third register, and the retracting the content of the third register corresponding to the retraction of the content of said second register.

Claim 11

A processor system, comprising: a main storage for storing data and instructions, at least some instructions having an operation code and an operand part including a register designating part, and wherein said instructions are part of a program which contains a plurality of subprograms, and further including a save area for the operations of saving data therein or restoring data therefrom; first means for decoding instructions of said program; a plurality of first registers which are allocated to said program, and at least some of first registers forming a plurality of multi-register areas each of which is selectively allocated to said subprograms; a second register storing information which identifies one of said multi-register areas allocated to one of said subprograms and the content of which is controlled by the operation code of instructions decoded by said first means, wherein one of the registers in said multi-register area identified by said second register is specified by said register designating part; a third register for indicating a position of one of said multi-register areas of said first registers for triggering said data saving or restoring operations, wherein the operation codes of some instructions indicate operations in which the content of said second register is advanced or retracted, or a subprogram is called from a current subprogram or the current subprogram is returned to a previous subprogram; and processing means for processing instructions according to decoded operation codes and contents of registers indicated by said second register and specified by decoded register designating parts, including means responsive to all of said multi-register areas being occupied by subprograms, as indicated by a determination of correspondence between the contents of said second and third registers as a result of said advancing or calling operations, for saving the content of the multi-register area specified by the content of said third register to said save area of said main storage, and for advancing the content of the third register corresponding to the advance of the content of said second register, and means responsive to determination of correspondence between the contents of said second and third registers as a result of said retracting or returning operations for restoring data from said save area of said main storage to the multi-register area specified by the content of said third register, and the retracting the content of the third register corresponding to the retraction of the content of said second register.

Claim 12

A processor system according to claim 8, wherein instructions whose operation codes indicate that the content of said second register is to be advanced or to be retracted are instructions different from instructions whose operation codes indicate that a subprogram is to be called from a current subprogram or that the current subprogram is to be returned to a previous subprogram.

Claim 13

A processor system according to claim 8, wherein a multi-register area allocated to a subprogram has a register to hold register save-indications that indicate which first registers contained in said multi-register area contain information to be retained for said subprogram and said processing means operates, when said saving or restoring operation is performed, to save or restore only the contents of the first registers indicated by said save-indications.

Claim 14

A processor system according to claim 8, wherein the operation codes of other instructions processed by said processing unit indicate that the contents of a plurality of said multi-register areas comprising said first registers are to be saved to or restored from said save area.

Claim 15

A processor system according to claim 8, wherein the operation code of another instruction indicates that the contents of said first registers contained in multi-register areas starting from a multi-register area indicated by said second register and ending with a multi-register area indicated by said third register are to be saved to said save area.

Claim 16

A processor system according to claim 8, wherein said first means for decoding instruction, said plurality of first registers and said processing means are fabricated on a single semiconductor chip as a microprocessor.

Claim 17

A processor system according to claim 8, wherein said first registers are addressable registers disposed in sequence in a ring-bank configuration.

Claim 18

A processor system according to claim 14, wherein the content of said second register represents a first pointer which indicates a multi-register area substantially entirely ahead of said first pointer within the ring-bank of first registers.

Claim 19

A processor system according to claim 15, further including a fourth register whose content represents a second pointer behind said first pointer and which indicates a multi-register area located between the first and second pointers.

Claim 20

A processor system, comprising: a main storage for storing data and instructions having an operation code part, some of said instructions having a register designating part and/or a main storage designating part, said instructions forming a plurality of programs at least one of which contains a plurality of subprograms; first means for decoding instructions of said program; a plurality of registers, a plurality of first groups of which are allocated respectively to respective ones of said plurality of programs, and at least one second group of which is divided into multi-register areas which are selectively allocated to subprograms corresponding to one of said programs, where the number of second groups is less than the number of first groups of said registers; second means for specifying a register by the content of one of said registers specified by one field of a register designating part of a decoded instruction and a displacement value specified by another field of said register designating part of said decoded instruction; and processing means for processing said instructions according to the operation code thereof and the content of the register specified by said second means when said instruction has a register designating part, and data from said main storage when said instruction has a main storage designating part, whereby different ones of said programs allotted to respective ones of said first groups of registers can be executed asynchronously without requiring save/restore operations and subprograms corresponding to said one of said programs and allocated respectively to said multi-register areas of said second group of registers can be executed with a reduced number of save/restore operations by selected register designation under instruction control.

Claim 21

A processor system, comprising: a main storage for storing data and instructions having an operation code part, some of said instructions having a register designating part and/or a main storage designating part, said instructions forming a plurality of programs at least one of which contains a plurality of subprograms; first means for decoding instructions of said program; a plurality of registers, a plurality of first groups of which are allocated respectively to respective ones of said plurality of programs, and at least one second group of which is divided into multi-register areas which are selectively allocated to subprograms corresponding to one of said programs, where the number of second groups is less than the number of first groups of said registers; second means for specifying a register by the content of one of said registers specified by one field of a register designating part of a decoded instruction and a displacement value specified by another field of said register designating part of said decoded instruction; and processing means for processing said instructions according to the operation code thereof and the content of the register specified by said second means when said instruction has a register designating part, and data from said main storage when said instruction has a main storage designating part, whereby different ones of said programs allotted to respective ones of said first groups of registers can be executed asynchronously without requiring save/restore operations and subprograms corresponding to said one of said programs and allocated respectively to said multi-register areas of said second group of registers can be executed with a reduced number of save/restore operations by selected register designation under instruction control.

Claim 22

A processor system according to claim 17, wherein said second groups of registers are addressable registers disposed in sequence in a ring-bank configuration.

Claim 23

A processor system according to claim 17, wherein said first means for decoding instructions, said plurality of first registers and said processing means are fabricated on a single semiconductor chip as a microprocessor.

Claim 24

A processor system, comprising: a main storage for storing data and instructions having an operation code part, some of said instructions having a register designating part and/or a main storage designating part, said instructions forming a plurality of programs at least one of which contains a plurality of subprograms; first means for decoding instructions; a plurality of first registers, a plurality of first groups of which are allocated respectively to respective ones of said plurality of programs, and at least one second group of which is divided into multi-register areas which are selectively allocated to subprograms corresponding to one of said programs; a second register for storing information which indicates one of said multi-register areas allocated to one of said subprograms and the content of which is controlled by the operation code of instructions decoded by said first means, wherein one of the registers in said register area identified by said second register is specified by said register designating part; second means for specifying a register by the content of one of said registers specified by one field of a register designating part of a decoded instruction and a displacement value specified by another field of said register designating part of said decoded instruction; and processing means for processing said instructions according to the operation code thereof and the content of the register specified by the decoded register designating part and included in the multi-register area indicated by the information stored in said second register, whereby different ones of said programs allotted to respective ones of said first groups of registers can be executed asynchronously without requiring save/restore operations and subprograms corresponding to said one of said programs and allocated respectively to said multi-register areas of said second group of registers can be executed with a reduced number of save/restore operations by selected register designation under instruction control; wherein the operation codes of some instructions indicate operations in which the content of said second register is to be advanced or retracted or in which a subprogram is called from a current subprogram or in which the current subprogram is returned to a previous subprogram.

Claim 25

A processor system, comprising: a main storage for storing data and instructions having an operation code part, some of said instructions having a register designating part and/or a main storage designating part, said instructions forming a plurality of programs at least one of which contains a plurality of subprograms; first means for decoding instructions; a plurality of first registers, a plurality of first groups of which are allocated respectively to respective ones of said plurality of programs, and at least one second group of which is divided into multi-register areas which are selectively allocated to subprograms corresponding to one of said programs; a second register for storing information which indicates one of said multi-register areas allocated to one of said subprograms and the content of which is controlled by the operation code of instructions decoded by said first means, wherein one of the registers in said register area identified by said second register is specified by said register designating part; second means for specifying a register by the content of one of said registers specified by one field of a register designating part of a decoded instruction and a displacement value specified by another field of said register designating part of said decoded instruction; and processing means for processing said instructions according to the operation code thereof and the content of the register specified by the decoded register designating part and included in the multi-register area indicated by the information stored in said second register, whereby different ones of said programs allotted to respective ones of said first groups of registers can be executed asynchronously without requiring save/restore operations and subprograms corresponding to said one of said programs and allocated respectively to said multi-register areas of said second group of registers can be executed with a reduced number of save/restore operations by selected register designation under instruction control; wherein the operation codes of some instructions indicate operations in which the content of said second register is to be advanced or retracted or in which a subprogram is called from a current subprogram or in which the current subprogram is returned to a previous subprogram.

Claim 26

A processor system according to claim 20, further comprising indicating means for indicating a number of said first groups of said first registers and a number of multi-register areas of said second group of said first registers, and wherein certain instructions having operation codes which indicate that the state of said indicating means is to be changed so as to change the number of said groups of said first registers and the number of said multi-register areas of said second group of said first registers; said processing means including means responsive to said certain instructions for changing the state of said indicating means.

Claim 27

A processor system according to claim 20, wherein said first means for decoding instructions, said plurality of first registers and said processing means are fabricated on a single semiconductor chip as a microprocessor.

Claim 28

A processor system according to claim 20, wherein said second group of first registers are addressable registers disposed in sequence in a ring-bank configuration.

Claim 29

A processor system according to claim 20, wherein said second means includes means for effecting an OR operation between the information stored in said second register and a displacement value specified by the register designating part of said instruction to produce a register indication having an upper part corresponding to an upper part of the information stored in said second register and a lower part formed by an OR operation between a lower part of the information stored in said second register and said displacement value.

Claim 30

A processor system according to claim 24, wherein one or more significant bit positions of said lower part of the information stored in said second register have a zero value when corresponding bit positions of said displacement part of said instruction provide register designating information, and one or more significant bit positions of said displacement value are zero when corresponding bit positions of said lower part of said second register provide multi-register area designating information; whereby the number of registers forming said multi-register areas may be selectively varied according to the information stored in said second register and the displacement value specified by the register designating part of said instruction.

Claim 31

A processor system according to claim 20, further comprising a third register for storing information which indicates a group of said first groups of first registers.

Claim 32

A processor system according to claim 26, further comprising a fourth register for storing information which indicates a multi-register area located behind the multi-register area indicated by said second register.

Claim 33

A processor system, comprising: a main storage for storing data and instructions having an operation code part, some of said instructions having a register designating part, and at least one of said instructions having both a register designating part and a main storage designating part; first means for decoding instructions; a plurality of registers grouped to form a plurality of multi-register areas; a plurality of multi-register area designating means each for storing information designating one of said multi-register areas; second means for specifying a register by the content of one of said multi-register area designating means specified by one field of a register designating part of a decoded instruction and a displacement value specified by another field of said register designating part of said decoded instruction, whereby switching between multi-register areas may be effected by selecting respective multi-register area designating means under instruction control; and processing means for processing said instructions according to the operation code thereof and the content of the register specified by said second means when said instruction has a register designating part and data from said main storage when said instruction has a main storage designating part.

Claim 34

A processor system, comprising: a main storage for storing data and instructions having an operation code part, some of said instructions having a register designating part, and at least one of said instructions having both a register designating part and a main storage designating part; first means for decoding instructions; a plurality of registers grouped to form a plurality of multi-register areas; a plurality of multi-register area designating means each for storing information designating one of said multi-register areas; second means for specifying a register by the content of one of said multi-register area designating means specified by one field of a register designating part of a decoded instruction and a displacement value specified by another field of said register designating part of said decoded instruction, whereby switching between multi-register areas may be effected by selecting respective multi-register area designating means under instruction control; and processing means for processing said instructions according to the operation code thereof and the content of the register specified by said second means when said instruction has a register designating part and data from said main storage when said instruction has a main storage designating part.

Claim 35

A processor system according to claim 28, wherein said second means includes means for effecting an OR operation between the content of one of said multi-register area designating means specified by one field of a register designating part of a decoded instruction and a displacement value specified by another field of said register designating part of said decoded instruction.

Claim 36

A process system according to claim 28, wherein said processing means includes means responsive to the operation code of certain instructions for setting in each multi-register area designating means information from said certain instructions for designating a multi-register area.

Claim 37

A processor system according to claim 28, wherein said first means for decoding instructions, said plurality of first registers and said processing means are fabricated on a single semiconductor chip as a microprocessor.

Claim 38

A processor system, comprising: a main storage for storing data and instructions, some of said instructions having an operation code and an operand part including a register designating part, and wherein said instructions form a program which contains a plurality of subprograms; first means for decoding instructions of said program; a plurality of first registers which are allocated to said program, and at least some of said first registers forming a plurality of multi-register areas, each of which is selectively allocated to said subprograms; a second register storing a pointer which indicates one of said multi-register areas allocated to one of said subprograms and the content of which is controlled by the operation code of instructions decoded by said first means, wherein one of the registers in said multi-register area identified by said second register is specified by said register designating part of an instruction; and processing means for processing instructions according to decoded operation codes and the content of registers in the multi-register area identified by the pointer stored in said second register and specified by decoded register designating parts, and including means responsive to operation codes of other instructions calling a subprogram from a current subprogram without advancement of the pointer stored in said second register or returning a current subprogram to a previous subprogram without retraction of the pointer stored in said second register, so that at least one of said subprograms, which does not have an instruction including an operation code for advancing or retracting the pointer stored in said second register, will share a multi-register area with at least one other subprogram.

Claim 39

A processor system, comprising: a main storage for storing data and instructions, some of said instructions having an operation code and an operand part including a register designating part, and wherein said instructions form a program which contains a plurality of subprograms; first means for decoding instructions of said program; a plurality of first registers which are allocated to said program, and at least some of said first registers forming a plurality of multi-register areas, each of which is selectively allocated to said subprograms; a second register storing a pointer which indicates one of said multi-register areas allocated to one of said subprograms and the content of which is controlled by the operation code of instructions decoded by said first means, wherein one of the registers in said multi-register area identified by said second register is specified by said register designating part of an instruction; and processing means for processing instructions according to decoded operation codes and the content of registers in the multi-register area identified by the pointer stored in said second register and specified by decoded register designating parts, and including means responsive to operation codes of other instructions calling a subprogram from a current subprogram without advancement of the pointer stored in said second register or returning a current subprogram to a previous subprogram without retraction of the pointer stored in said second register, so that at least one of said subprograms, which does not have an instruction including an operation code for advancing or retracting the pointer stored in said second register, will share a multi-register area with at least one other subprogram.

Claim 40

A processor system according to claim 32, wherein said first registers are addressable registers disposed in sequence in a ring-bank configuration.

Claim 41

A processor system according to claim 32, wherein said first means for decoding instructions, said plurality of first registers and said processing means are fabricated on a single semiconductor chip as a microprocessor.