Pipelined split stack with high performance interleaved decode

Claim 2

For use in a high performance storage unit capable of pipeline interaction with multiple requesting units, and having a plurality of addressable memory banks, memory bank access control circuitry for decoding, prioritizing, and issuing bank acknowledge signals in response to applied bank selection signals, a clock signals distributed in the unit, and capable of pipelining up to R requests for access to the memory banks without having received an acknowledge signal indicating that an access has been completed, a high performance virtual first-in first-out pipelined data stack structure comprising: request receiving means for receiving request in signals from an associated requester; bank acknowledge receiving means for receiving bank acknowledge signals; interface means for receiving data words to be written in memory banks at addressable locations; split control stack means including a first set of 1/2R split stack register means and a second set of 1/2R split stack register means, said first and second sets of split stack register means for alternately storing sequential bank selection signals and request in signals between said first set and said second set; split control stack write control means responsively coupled to said request in receiving means for causing said bank selection signals to be alternately stored in successively addressed ones of said split stack register means in response to successive ones of said request in signals; split control stack read control means coupled to said bank acknowledge receiving means for causing alternate readout from successively addressed ones of said split stack register means.

Claim 3

A split control stack as in claim 1 wherein said split stack write pointer means comprises: write enable shift register means coupled to said request receiving means and having output terminals each for enabling an associated one of said split control stack register means alternating said enabling between said first set and said second set in response to successive ones of said request in signals.

Claim 4

A split control stack as in claim 1 wherein said split control stack read control means includes: first read address pointer means coupled to said first set of split control stack registers for enabling read out of the selected one of said first set of split control stack registers; and second read address pointer means coupled to said second set of split control stack registers for enabling read out of the selected one of said second set of split control stack registers.

Claim 5

A split control stack as in claim 3 wherein said split control stack read control means further includes: read address pointer control means responsively coupled to said bank acknowledge receiving means for alternately advancing said first read address pointer means and said second read address pointer means for interleaving selection of memory bank selection signals from said first and said second sets of split control stack registers.

Claim 6

In a high performance storage unit having a plurality of addressable memory banks, bank priority and bank decoding selection circuits operative to provide bank acknowledge signals in response to bank request signals, a pipelined data stack for storing data words, addresses, and function relative to said memory banks, a split control stack comprising: request receiving means for receiving requests for access to the memory banks; input means for receiving data input signals indicative at least in part of memory banks selection signals associated with data words addressed; a first set and a second set of split control stack register means, each of said split control stack register means for storing associated ones of said memory bank selection signals; split stack write pointer means coupled to said request receiving means for alternating sequential storage of said memory bank selection signals in said split control stack registers in said first set and said second sets; first read address pointer means coupled to said first set of split control stack registers for enabling read out of the selected one of said first set of split control stack registers; second read address pointer means coupled to said second set of split control stack registers for enabling read out of the selected one of said second set of split control stack registers; bank acknowledge receiving means for receiving bank acknowledge signals; read address pointer control means responsively coupled to said bank acknowledge receiving means for alternately advancing said first read address pointer means and said second read address pointer means for interleaving selection of memory bank selection signals from said first and said second set of split control stack registers.

Claim 7

In a high performance storage unit having a plurality of addressable memory banks, bank priority and bank decoding selection circuits operative to provide bank acknowledge signals in response to bank request signals, a pipelined data stack for storing data words, addresses, and function relative to said memory banks, a split control stack comprising: request receiving means for receiving requests for access to the memory banks; input means for receiving data input signals indicative at least in part of memory banks selection signals associated with data words addressed; a first set and a second set of split control stack register means, each of said split control stack register means for storing associated ones of said memory bank selection signals; split stack write pointer means coupled to said request receiving means for alternating sequential storage of said memory bank selection signals in said split control stack registers in said first set and said second sets; first read address pointer means coupled to said first set of split control stack registers for enabling read out of the selected one of said first set of split control stack registers; second read address pointer means coupled to said second set of split control stack registers for enabling read out of the selected one of said second set of split control stack registers; bank acknowledge receiving means for receiving bank acknowledge signals; read address pointer control means responsively coupled to said bank acknowledge receiving means for alternately advancing said first read address pointer means and said second read address pointer means for interleaving selection of memory bank selection signals from said first and said second set of split control stack registers.

Claim 8

A split control stack as in claim 5 wherein said split stack write pointer means comprises: write enable shift register means coupled to said request receiving means and having output terminals for enabling associated ones of said split control stack register means alternating said enabling between said first set and said second set in response to successive ones of said request in signals.

Claim 9

A split control stack as in claim 6 wherein said first read address pointer means and said second address pointer means each comprise: read enable shift register means coupled for enabling read out of associated ones of said split control stack register means and coupled to said read address pointer control means for advancing said read enable shift register means in response to alternate ones of said memory bank acknowledge signals.

Claim 10

For use in a high performance storage unit capable of pipelined interaction with multiple requesting units, and having a plurality of addressable memory banks, memory bank access control circuitry for decoding, prioritizing, and issuing bank acknowledge signals in response to applied bank selection signals, a source of clock signal distributed in the unit, and capable of pipelining up to R requests for access to the memory banks without having received an acknowledge signal indicating that an access has been completed, a high performance virtual first-in first-out pipelined stack structure comprising: request receiving means for receiving request in signals from an associated requester; bank acknowledge receiving means for receiving bank acknowledge signals; interface means for receiving data words to be written in memory banks at addressable locations; clock signal receiving means for receiving predetermined ones of the clock signals for timing operation of the structure; data stack means coupled to said interface means and said clock signal receiving means for receiving data words and at least temporarily storing said data words when enabled by predetermined ones of the clock signals, pending availability of access to the selected memory banks, said data stack means including R+1 data stack register means for protecting at least R ones of said data stack register means against over-write at all times; data stack write pointer means coupled to said data stack means for providing write address signals indicative of said R+1 data stack register means in a predetermined order and for enabling storage of the data words therein, and having write pointer advance means coupled to said request receiving means for advancing said data stack write pointer means for advancing said data stack write pointer means to address the next sequential one of said R+1 data stack register means in response to each request in signal received; data stack read pointer means coupled to said data stack means for providing read address signals indicative of said R+1 data stack register means in a predetermined order, and having read pointer advance means coupled to said bank acknowledge receiving means for advancing said data stack read pointer means to address the next sequential one of said R+1 data stack register means in response to each bank acknowledge signal received; data stack read decoder means responsively coupled to said data stack read pointer means for decoding said read address signals and enabling the read out of the selected ones of said R+1 data stack register means in response thereto; a first set and a second set of split control stack register means, each of said split control stack register means for storing associated ones of said memory bank selection signals; split stack write pointer means coupled to said request receiving means for alternating sequential storage of said memory bank selection signals in said split control stack registers in said first set and said second sets; first read address pointer means coupled to said first set of split control stack registers for enabling read out of the selected one of said first set of split control stack registers; second read address pointer means coupled to said second set of split control stack registers for enabling read out of the selected one of said second set of split control stack registers; and split control stack read address pointer control means responsively coupled to said bank acknowledge receiving means for alternately advancing said first read address pointer means and said second read address pointer means for interleaving selection of memory bank selection signals from said first and said second set of split control stack registers.

Claim 11

For use in a high performance storage unit capable of pipelined interaction with multiple requesting units, and having a plurality of addressable memory banks, memory bank access control circuitry for decoding, prioritizing, and issuing bank acknowledge signals in response to applied bank selection signals, a source of clock signal distributed in the unit, and capable of pipelining up to R requests for access to the memory banks without having received an acknowledge signal indicating that an access has been completed, a high performance virtual first-in first-out pipelined stack structure comprising: request receiving means for receiving request in signals from an associated requester; bank acknowledge receiving means for receiving bank acknowledge signals; interface means for receiving data words to be written in memory banks at addressable locations; clock signal receiving means for receiving predetermined ones of the clock signals for timing operation of the structure; data stack means coupled to said interface means and said clock signal receiving means for receiving data words and at least temporarily storing said data words when enabled by predetermined ones of the clock signals, pending availability of access to the selected memory banks, said data stack means including R+1 data stack register means for protecting at least R ones of said data stack register means against over-write at all times; data stack write pointer means coupled to said data stack means for providing write address signals indicative of said R+1 data stack register means in a predetermined order and for enabling storage of the data words therein, and having write pointer advance means coupled to said request receiving means for advancing said data stack write pointer means for advancing said data stack write pointer means to address the next sequential one of said R+1 data stack register means in response to each request in signal received; data stack read pointer means coupled to said data stack means for providing read address signals indicative of said R+1 data stack register means in a predetermined order, and having read pointer advance means coupled to said bank acknowledge receiving means for advancing said data stack read pointer means to address the next sequential one of said R+1 data stack register means in response to each bank acknowledge signal received; data stack read decoder means responsively coupled to said data stack read pointer means for decoding said read address signals and enabling the read out of the selected ones of said R+1 data stack register means in response thereto; a first set and a second set of split control stack register means, each of said split control stack register means for storing associated ones of said memory bank selection signals; split stack write pointer means coupled to said request receiving means for alternating sequential storage of said memory bank selection signals in said split control stack registers in said first set and said second sets; first read address pointer means coupled to said first set of split control stack registers for enabling read out of the selected one of said first set of split control stack registers; second read address pointer means coupled to said second set of split control stack registers for enabling read out of the selected one of said second set of split control stack registers; and split control stack read address pointer control means responsively coupled to said bank acknowledge receiving means for alternately advancing said first read address pointer means and said second read address pointer means for interleaving selection of memory bank selection signals from said first and said second set of split control stack registers.

Claim 12

A stack structure as in claim 8 wherein said split stack write pointer means comprises: write enable shift register means coupled to said request receiving means and having output terminals for enabling associated ones of said split control stack register means alternating said enabling between said first set and said second set in response to successive ones of said request in signals.

Claim 13

A stack structure as in claim 8 wherein said first read address pointer means and said second address pointer means each comprise: read enable shift register means coupled for enabling read out of associated ones of said split control stack register means and coupled to said read address pointer control means for advancing said read enable shift register means is response to alternate ones of said memory bank acknowledge signals.

Claim 14

A data stack structure as in claim 8 wherein said data stack write pointer means includes: shift register means having R+1 stages interconnected for advancing said write address signals in a predetermined order in response to said request in signals.

Claim 15

A data stack structure as in claim 8 wherein said data stack read pointer means includes: read counter means for circularly counting in response to said bank acknowledge signals and first ones of said clock signals, and for providing R+1 ones of said read address signals, each for addressing an associated one of said R+1 stack register means.

Claim 16

A data stack structure as in claim 8 wherein said data stack read decoder means includes: decode circuits means responsively coupled to said read counter means for providing R+1 unique read enable signals in response to said address signals.