Wraparound buffer for repetitive decimal numeric operations

Claim 2

In a data processing system, having a main storage element for storing programs and data utilized by a central processing unit (CPU) of said data processing system, said CPU executing the programs stored in the main storage element, said CPU being operatively connected to said main storage element, and wherein the CPU includes a central unit, a cache unit, and a plurality of execution units, the cache unit storing instructions and operands currently awaiting execution, the cache unit being operatively connected to the main storage element, and the central unit performing predetermined initial operations on the instructions, the initial operations including fetching instructions from said cache unit, decoding the instructions, preparing the virtual address, paging and fetching the operand associated with the instruction, and transferring the instruction to a predetermined one of the execution units, each execution unit performing the execution of a predetermined class of instruction, each execution unit being operatively connected to said cache unit for receiving operands and to said central unit for receiving predetermined instructions processed by said central unit, wherein at least one execution unit includes a first stage, operatively connected to said central unit and to said cache unit, for temporarily storing input data, said input data being predetermined instructions including operation commands from said central unit and the operand being received from said cache unit, and a second stage, having two inputs for receiving two operands, operatively connected to said first stage for executing the predetermined instruction, and wherein the first stage includes a first input buffer for temporarily storing at least one predetermined instruction, and a second input buffer for temporarily storing the operand associated with said temporarily stored predetermined instruction to distribute said temporarily stored operand to the second stage, said second input buffer comprising: (a) first storage means, operatively connected to said cache unit, for temporarily holding said operand; (b) second storage means, operatively connected to an output of said second stage, for temporarily holding result data from the completed execution of the instruction by said second stage; (c) control logic means, operatively connected to said first input buffer, for generating select control signals; and (d) switch means, operatively connected to said first storage means and to said second storage means, and further operatively connected to said second stage, for selectively coupling the operand stored in said first storage means or the result data stored in said second storage means to said second stage to be utilized in the execution of the next sequential instruction from the completed instruction which yielded the result data, in response to said select control signals.

Claim 3

In a data processing system, having a main storage element for storing programs and data utilized by a central processing unit (CPU) of said data processing system, said CPU executing the programs stored in the main storage element, said CPU being operatively connected to said main storage element, and wherein the CPU includes a central unit, a cache unit, and a plurality of execution units, the cache unit storing instructions and operands currently awaiting execution, the cache unit being operatively connected to the main storage element, and the central unit performing predetermined initial operations on the instructions, the initial operations including fetching instructions from said cache unit, decoding the instructions, preparing the virtual address, paging and fetching the operand associated with the instruction, and transferring the instruction to a predetermined one of the execution units, each execution unit performing the execution of a predetermined class of instruction, each execution unit being operatively connected to said cache unit for receiving operands and to said central unit for receiving predetermined instructions processed by said central unit, wherein at least one execution unit includes a first stage, operatively connected to said central unit and to said cache unit, for temporarily storing input data, said input data being predetermined instructions including operation commands from said central unit and the operand being received from said cache unit, and a second stage, having two inputs for receiving two operands, operatively connected to said first stage for executing the predetermined instruction, and wherein the first stage includes a first input buffer for temporarily storing at least one predetermined instruction, and a second input buffer for temporarily storing the operand associated with said temporarily stored predetermined instruction to distribute said temporarily stored operand to the second stage, said second input buffer comprising: (a) first storage means, operatively connected to said cache unit, for temporarily holding a first operand; (b) second storage means, operatively connected to said cache unit, for temporarily holding a second operand; (c) third storage means, operatively connected to an output of said second stage, for temporarily holding result data from the completed execution of the instruction by said second stage; (d) control logic means, operatively connected to said first input buffer, for generating select control signals; and (e) switch means, operatively connected to said first, second and third storage means, and further operatively connected to said second stage, for selectively coupling the operand stored in said first storage means or said second storage means, or the result data stored in said third storage means, to said second stage to be utilized in the execution of the next sequential instruction from the completed instruction which yielded the result data, in response to said select control signals.

Claim 4

In a data processing system, having a main storage element for storing programs and data utilized by a central processing unit (CPU) of said data processing system, said CPU executing the programs stored in the main storage element, said CPU being operatively connected to said main storage element, and wherein the CPU includes a central unit, a cache unit, and a plurality of execution units, the cache unit storing instructions and operands currently awaiting execution, the cache unit being operatively connected to the main storage element, and the central unit performing predetermined initial operations on the instructions, the initial operations including fetching instructions from said cache unit, decoding the instructions, preparing the virtual address, paging and fetching the operand associated with the instruction, and transferring the instruction to a predetermined one of the execution units, each execution unit performing the execution of a predetermined class of instruction, each execution unit being operatively connected to said cache unit for receiving operands and to said central unit for receiving predetermined instructions processed by said central unit, wherein at least one execution unit includes a first stage, operatively connected to said central unit and to said cache unit, for temporarily storing input data, said input data being predetermined instructions including operation commands from said central unit and the operand being received from said cache unit, and a second stage, having two inputs for receiving two operands, operatively connected to said first stage for executing the predetermined instruction, and wherein the first stage includes a first input buffer for temporarily storing at least one predetermined instruction, and a second input buffer for temporarily storing the operand associated with said temporarily stored predetermined instruction to distribute said temporarily stored operand to the second stage, said second input buffer comprising: (a) first storage means, operatively connected to said cache unit, for temporarily holding a first operand; (b) second storage means, operatively connected to said cache unit, for temporarily holding a second operand; (c) third storage means, operatively connected to an output of said second stage, for temporarily holding result data from the completed execution of the instruction by said second stage; (d) control logic means, operatively connected to said first input buffer, for generating select control signals; and (e) switch means, operatively connected to said first, second and third storage means, and further operatively connected to said second stage, for selectively coupling the operand stored in said first storage means or said second storage means, or the result data stored in said third storage means, to said second stage to be utilized in the execution of the next sequential instruction from the completed instruction which yielded the result data, in response to said select control signals.