US3794980A
Expired / Lapsed
US
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Apparatus and method for controlling sequential execution of instructions and nesting of subroutines in a data processor
Assignee: Cogar Corp
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Filing: 1971-04-21
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Granted: 1974-02-26
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Expires: 1991-04-21
Abstract
Abstract A stack pointer for identifying one of a group of instruction word address registers in a data processor. To fetch a new instruction, the stack pointer is examined to identify the instruction word address register to be used. The address contained in this register is then incremented to derive the address of the new instruction to be executed. A branch instruction causes the stack pointer to be incremented and the base address of the new subroutine to be loaded into the instruction word address register newly identified by the stack pointer. An exit instruction causes the stack pointer to be decremented. Exit-and-branch instructions are possible because the stack pointer counts in a closed loop in both directions, there being no ''''first'''' or ''''last'''' instruction word address register.
Inventors
- 👤 G Cogar
- 👤 A Huyck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:51
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/321; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484; G06F9/4486
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
111 words
A data processor comprising a memory having instructions stored therein at successively addressed locations, a plurality of instruction word address registers, stack pointer means having a plurality of states each associated with a respective one of said instruction word address registers, the states of said stack pointer means following each other in a closed loop sequence in both directions, means for advancing the state of said stack pointer means in a fixed sequence in each direction, and means for determining the address of an instruction to be executed from the address contained in that one of said instruction word address registers whose associated state is represented by said stack pointer means.
Claim 2
Dependent Claim
111 words
A data processor comprising a memory having instructions stored therein at successively addressed locations, a plurality of instruction word address registers, stack pointer means having a plurality of states each associated with a respective one of said instruction word address registers, the states of said stack pointer means following each other in a closed loop sequence in both directions, means for advancing the state of said stack pointer means in a fixed sequence in each direction, and means for determining the address of an instruction to be executed from the address contained in that one of said instruction word address registers whose associated state is represented by said stack pointer means.
Claim 3
Dependent Claim
42 words
A data processor in accordance with claim 1 further including means for incrementing the address contained in the instruction word address register represented by said stack pointer means each time an instruction is executed so that successively addressed instructions can be executed.
Claim 4
Dependent Claim
29 words
examining the contents of the instruction word address register whose associated system state is identified in step (1) to determine the address of an instruction to be executed, and
Claim 5
Dependent Claim
29 words
examining the contents of the instruction word address register whose associated system state is identified in step (1) to determine the address of an instruction to be executed, and
Claim 6
Dependent Claim
29 words
examining the contents of the instruction word address register whose associated system state is identified in step (1) to determine the address of an instruction to be executed, and
Claim 7
Dependent Claim
29 words
examining the contents of the instruction word address register whose associated system state is identified in step (1) to determine the address of an instruction to be executed, and
Claim 8
Dependent Claim
81 words
A data processor comprising means for storing instructions at respectively addressed locations, a plurality of instruction word address register means, circularly-operating stack pointer means for representing a plurality of sequentially selectable states each associated with a respective one of said instruction word address register means, and means for determining the address of an instruction to be executed from the address contained in that one of said instruction word address register means whose associated state is represented by said stack pointer means.
Claim 9
Dependent Claim
81 words
A data processor comprising means for storing instructions at respectively addressed locations, a plurality of instruction word address register means, circularly-operating stack pointer means for representing a plurality of sequentially selectable states each associated with a respective one of said instruction word address register means, and means for determining the address of an instruction to be executed from the address contained in that one of said instruction word address register means whose associated state is represented by said stack pointer means.
Claim 10
Dependent Claim
50 words
changing the system state identified in step (1) to control a transfer to or from a subroutine, said system states having an order such that a change in either of two directions from one of said system states causes a different respective one of said system states to be identified.
Claim 11
Dependent Claim
50 words
changing the system state identified in step (1) to control a transfer to or from a subroutine, said system states having an order such that a change in either of two directions from one of said system states causes a different respective one of said system states to be identified.
Claim 12
Dependent Claim
52 words
changing the system state identified in step 1 to control a transfer to or from a subroutine, said system states having a closed-loop order such that a change in either of two directions from each one of said systems states causes a different respective one of said system states to be identified.
Claim 13
Dependent Claim
52 words
changing the system state identified in step 1 to control a transfer to or from a subroutine, said system states having a closed-loop order such that a change in either of two directions from each one of said systems states causes a different respective one of said system states to be identified.
Claim 14
Dependent Claim
45 words
storing a base address in an instruction word address register when the system state identified in step (1) is first changed to the system state associated with the instruction word address register. 8, A method in accordance with claim 7 further including the step of:
Claim 15
Dependent Claim
48 words
A data processor in accordance with claim 3 further including means for selectively incrementing the address contained in the instruction word address register means whose associated state is represented by said stack pointer means each time an instruction is executed so that successively addressed instructions can be executed.
Claim 16
Dependent Claim
32 words
storing a base address in an instruction word address register when the system state idetified in step (1) is first changed to the system state associated with the instruction word address register.
Claim 17
Dependent Claim
32 words
storing a base address in an instruction word address register when the system state idetified in step (1) is first changed to the system state associated with the instruction word address register.
Claim 18
Dependent Claim
27 words
selectively inhibiting the performance of step (4) and instead incrementing the address contained in the instruction word address register whose associated number is identified in step (1).
Claim 19
Dependent Claim
27 words
selectively inhibiting the performance of step (4) and instead incrementing the address contained in the instruction word address register whose associated number is identified in step (1).
Claim 20
Dependent Claim
27 words
selectively inhibiting the performance of step (4) and instead incrementing the address contained in the instruction word address register whose associated number is identified in step (1).
Claim 21
Dependent Claim
27 words
selectively inhibiting the performance of step (4) and instead incrementing the address contained in the instruction word address register whose associated number is identified in step (1).
Claim 22
Independent Claim
53 words
A method for controlling the sequential execution of instructions by a data processor having instructions stored at respectively addressed locations, and a plurality of instruction word address registers, each of said instruction word address registers being associated with a respective one of a group of sequentially selectable system states, comprising the steps of:
Claim 23
Independent Claim
53 words
A method for controlling the sequential execution of instructions by a data processor having instructions stored at respectively addressed locations, and a plurality of instruction word address registers, each of said instruction word address registers being associated with a respective one of a group of sequentially selectable system states, comprising the steps of:
Claim 24
Dependent Claim
24 words
A method in accordance with claim 5 wherein step (2) includes incrementing the address contained in the instruction word address register which is examined.
Claim 25
Dependent Claim
12 words
A method in accordance with claim 5 further including the step of:
Claim 26
Dependent Claim
130 words
A data processor comprising means for storing instructions at respectively addressed locations, a plurality of instruction word Address register means, stack pointer means for representing a plurality of ordered states each associated with a respective one of said instruction word address register means, means for advancing the state of said stack pointer means in either of two directions, said states being ordered such that an advance from each one of said states in either of said two directions causes a different respective one of said states to be represented by said stack pointer means, and means for determining the address of an instruction to be executed from the address contained in that one of said instruction word address register means whose associated state is represented by said stack pointer means.
Claim 27
Dependent Claim
130 words
A data processor comprising means for storing instructions at respectively addressed locations, a plurality of instruction word Address register means, stack pointer means for representing a plurality of ordered states each associated with a respective one of said instruction word address register means, means for advancing the state of said stack pointer means in either of two directions, said states being ordered such that an advance from each one of said states in either of said two directions causes a different respective one of said states to be represented by said stack pointer means, and means for determining the address of an instruction to be executed from the address contained in that one of said instruction word address register means whose associated state is represented by said stack pointer means.
Claim 28
Dependent Claim
48 words
A data processor in accordance with claim 9 further including means for selectively incrementing the address contained in the instruction word address register means whose associated state is represented by said stack pointer means each time an instruction is executed so that successively addressed instructions can be executed.
Claim 29
Independent Claim
53 words
A method for controlling the sequential execution of instructions by a data processor having instructions stored at respectively addressed locations, and a plurality of instruction word address registers, each of said instruction word address registers being associated with a respective one of a group of sequentially selectable system states, comprising the steps of:
Claim 30
Independent Claim
53 words
A method for controlling the sequential execution of instructions by a data processor having instructions stored at respectively addressed locations, and a plurality of instruction word address registers, each of said instruction word address registers being associated with a respective one of a group of sequentially selectable system states, comprising the steps of:
Claim 31
Dependent Claim
24 words
A method in accordance with claim 11 wherein step (2) includes incrementing the address contained in the instruction word address register which is examined.
Claim 32
Dependent Claim
12 words
A method in accordance with claim 11 further including the step of:
Claim 33
Dependent Claim
12 words
A method in accordance with claim 13 further including the step of:
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-25 | 1977-08-27 | 1978-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-25 | 1981-08-27 | 1982-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-25 | 1985-08-27 | 1986-02-26 | $7700.00 | Window Closed / Lapsed |