US4079448A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for synchronizing tasks on peripheral devices
Assignee: Bull SAS
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Filing: 1975-04-07
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Granted: 1978-03-14
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Expires: 1995-04-07
Abstract
Abstract The disclosure describes an improved apparatus for simultaneously transferring data or commands between several peripheral devices and a central processing unit. The apparatus includes a peripheral control unit which links the central processing unit to several peripheral devices. The peripheral control unit operates as a master with respect to the central processing unit and the peripheral devices in order to increase the capacity of the central processing unit.
Inventors
- 👤 Ngoc Luyen N'Guyen
- 👤 Tuong Duc Luu
- 👤 Jean Maurice Finet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:49
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4843; G06F9/4881
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
338 words
In a data processing system comprising a central processing unit, a plurality of peripheral devices, a plurality of adaptor devices, each adaptor device associated with a respective one of said peripheral devices, and a peripheral control unit for selectively transmitting data between said central processing unit and said peripheral device, said peripheral control unit being arranged for controlling devices of channel microprocesses of at least a first class, and including means for storing said channel microprocesses, said channel microprocesses comprising said first class of microprocesses which have the properties of being automatically initiated at the start of an interrupt event and of being non-addressable by other microprocesses and are of first and second levels of priority, and a second class of microprocesses which is addressable by other microprocesses, said second class of microprocesses having varying levels of priorities, said peripheral control unit comprising: port means responsive to said adaptor devices for identifying microprocess characteristics, including the class and priority level of the channel microprocess which is being executed by one of said adaptor devices to transfer data between one of said peripheral devices and said central processing unit; coding means responsive to said port means for assinging priority levels to each of said first and second classes of channel microprocesses; means responsive to said coding means and to the characteristics of said channel microprocesses for enabling the channel microprocesses of the first priority level to interrupt microprocesses of the second class; dispatching means responsive to the priority level derived from said coding means for scanning said second class of channel microprocesses to select one of said second class of channel microprocesses having the highest level of priority, and for interrupting the channel microprocesses being run to transfer data and replacing it with the selected one microprocess if the priority level of the one selected channel microprocess is higher than the priority level of the channel microprocess being run currently; and means for completing the interrupted microprocess after the execution of the one selected channel microprocess has been terminated.
Claim 2
Dependent Claim
338 words
In a data processing system comprising a central processing unit, a plurality of peripheral devices, a plurality of adaptor devices, each adaptor device associated with a respective one of said peripheral devices, and a peripheral control unit for selectively transmitting data between said central processing unit and said peripheral device, said peripheral control unit being arranged for controlling devices of channel microprocesses of at least a first class, and including means for storing said channel microprocesses, said channel microprocesses comprising said first class of microprocesses which have the properties of being automatically initiated at the start of an interrupt event and of being non-addressable by other microprocesses and are of first and second levels of priority, and a second class of microprocesses which is addressable by other microprocesses, said second class of microprocesses having varying levels of priorities, said peripheral control unit comprising: port means responsive to said adaptor devices for identifying microprocess characteristics, including the class and priority level of the channel microprocess which is being executed by one of said adaptor devices to transfer data between one of said peripheral devices and said central processing unit; coding means responsive to said port means for assinging priority levels to each of said first and second classes of channel microprocesses; means responsive to said coding means and to the characteristics of said channel microprocesses for enabling the channel microprocesses of the first priority level to interrupt microprocesses of the second class; dispatching means responsive to the priority level derived from said coding means for scanning said second class of channel microprocesses to select one of said second class of channel microprocesses having the highest level of priority, and for interrupting the channel microprocesses being run to transfer data and replacing it with the selected one microprocess if the priority level of the one selected channel microprocess is higher than the priority level of the channel microprocess being run currently; and means for completing the interrupted microprocess after the execution of the one selected channel microprocess has been terminated.
Claim 3
Dependent Claim
76 words
Apparatus, as claimed in Claim 12, wherein said storing means comprises means for storing data assigning to each channel microprocess of the second class one of the three states comprising: a timer state indicating that the microprocess can be executed only after a predetermined time period has expired: a ready state indicating that the microprocess is ready to be executed at any time; and an unplanned state indicating that no state is planned for the microprocess.
Claim 4
Dependent Claim
26 words
Apparatus as claimed in Claim 2, wherein said storing means comprises means for storing an indicator word having a value proportional to the predetermined time period.
Claim 5
Dependent Claim
116 words
Apparatus as claimed in Claim 3, wherein said storing means comprises storage means for data organizing the channel microprocesses in the ready state having the same priority level into a queue of microprocesses, said storing means for organizing comprising: means for storing a head word that identifies the microprocess at the head of the queue; means for storing a tail word that identifies the microprocess at the tail of the queue; means for storing in connection with each microprocess in the queue a following indicator which identifies the following microprocess in the queue; and means for storing in connection with each microprocess in the queue a preceding indicator which identifies the preceding microprocess in the queue.
Claim 6
Dependent Claim
192 words
Apparatus, as claimed in 1, wherein said storing means comprises: a first memory field which contains a starting address for the execution of a first microprocess of the first class having the first level of priority associated with a first event signal received from a first one of said peripheral devices; a second memory field which identifies a working memory field for the execution of the first microprocess; a third memory field which contains a starting address for the execution of a second microprocess of the first class having the second level or priority associated with a second event signal received from said first peripheral device: a fourth memory field which identifies a working memory field for the execution of the second microprocess; a fifth memory field which contains the number of a logical channel associated with said first peripheral device, as well as the maximum number of logical channels connected to the first peripheral device; and a sixth memory field which includes a first bit signifying that the second event signal is masked and a second bit signifying that all of the operations on said first peripheral device have been stopped.
Claim 7
Dependent Claim
171 words
Apparatus, as claimed in Claim 5, wherein the channel microprocesses of the second class are represented by 2 n -2 levels and wherein said port means for identifying microprocess characteristics is responsive to data stored in locations of said storing means including: a first location for storing an NPC word in n bits which represents the priority level of the microprocess which is in the process of transferring data; a second location for storing an M bit indicative of a masked sequence which can temporarily place the microprocess in the process of transferring data at the second priority level; a third location for storing an L bit which indicates that said dispatching means is in the process of interrogating the tables of said dispatching means; a fourth location for storing a P bit which indicates that a microprocess is in the process of transferring data; and a fifth location for storing an F bit which signals that a microprocess has passed into the Ready queue of microprocesses ready to be executed.
Claim 8
Dependent Claim
45 words
Apparatus, as claimed in claim 5, and further comprising means responsive to the first event signal for reading a register containing a signal corresponding to said first peripheral device and for designating the starting address stored within said first memory field of said storing means.
Claim 9
Dependent Claim
72 words
Apparatus, as claimed in claim 7, and further comprising: means responsive to the first event signal for initiating the execution of the first microprocess; clock means for generating a periodic timer signal; means responsive to the periodic timer signal for determining that a predetermined microprocess is in the timer state, determining that the predetermined time period associated with the predetermined microprocess has expired, and placing the predetermined microprocess in the ready state.
Claim 10
Dependent Claim
49 words
Apparatus, as claimed in claim 8, and further comprising means for preventing a microprocess of the second class or a second level priority microprocess of the first class from interrupting and replacing a microprocess in the process of transferring data which has a first or second level of priority.
Claim 11
Dependent Claim
29 words
Apparatus, as claimed in claim 1, wherein said dispatching means further comprises means for executing microprocesses having a second level priority before executing a microprocess of the second class.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-13 | 1981-09-12 | 1982-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-13 | 1985-09-12 | 1986-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-13 | 1989-09-12 | 1990-03-14 | $7700.00 | Window Closed / Lapsed |