US3848233A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for interfacing with a central processing unit
Assignee: Bunker Ramo Corp
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Filing: 1971-11-01
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Granted: 1974-11-12
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Expires: 1991-11-01
Abstract
Abstract An interface unit for controlling the transfer of information between a plurality of data bearing lines, at least some of which are fed by input/output devices, and a central processing unit. Since information may be received at at least two different priority levels, the unit includes a means for detecting the priority level of received information. When the unit receives information, it stores the information in an addressable buffer memory in an area allocated to the particular priority level and informs the CPU that information at the priority level is available. The address at which the information is stored is determined from an input address memory which stores the address at which the next item of information at each priority level is to be placed. The CPU then interrogates the unit causing information to be transferred from the buffer memory to the CPU under control of an output address memory which contains the address in the buffer for each priority level of the next item to be transferred to the CPU. An output buffer memory is also provided in the unit. When the CPU indicates that it has data to transmit, data is loaded into this memory in a position corresponding to the intended device a character at a time. Each time the unit is ready for another character from the CPU, the CPU is informed of this fact.
Inventors
- 👤 D Jen
- 👤 A Lotan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 06:10
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
206 words
A unit for controlling the transfer of information between a plurality of data bearing lines, which lines are scanned in a predetermined sequence, and a central processing unit (CPU), said information having at least two different priority levels, said unit comprising: means for indicating the data bearing line being scanned at any given time; means for detecting the priority level of each item of information applied to said unit; means responsive to said detecting means for informing the CPU of the availability of information at the detected priority level; an addressable memory, said memory having an area allocated to each of said priority levels; input means for indicating the address in said memory at which the next item of information at each of said priority levels is to be stored; means responsive to said detecting and input indicating means for storing each applied item of information in said memory; output means for indicating the address in said memory at which is stored the next item of information at each of said priority levels to be transferred to said CPU; and means responsive at least in part to said informing means and said output means for transferring an item of information from said memory to said CPU.
Claim 2
Dependent Claim
206 words
A unit for controlling the transfer of information between a plurality of data bearing lines, which lines are scanned in a predetermined sequence, and a central processing unit (CPU), said information having at least two different priority levels, said unit comprising: means for indicating the data bearing line being scanned at any given time; means for detecting the priority level of each item of information applied to said unit; means responsive to said detecting means for informing the CPU of the availability of information at the detected priority level; an addressable memory, said memory having an area allocated to each of said priority levels; input means for indicating the address in said memory at which the next item of information at each of said priority levels is to be stored; means responsive to said detecting and input indicating means for storing each applied item of information in said memory; output means for indicating the address in said memory at which is stored the next item of information at each of said priority levels to be transferred to said CPU; and means responsive at least in part to said informing means and said output means for transferring an item of information from said memory to said CPU.
Claim 3
Dependent Claim
81 words
A unit of the type described in claim 1 wherein said informing means includes at least one element for each priority level; wherein the priority represented by each element of said informing means may be varied; and including means for indicating the priority level represented by each element of said informing means; and means responsive to the last mentioned indicating means for controlling the address in the output means utilized for each transfer of inFormation from said memory to said CPU.
Claim 4
Dependent Claim
22 words
A unit of the type described in claim 2 including means for permitting said controlling means to be controlled from the CPU.
Claim 5
Dependent Claim
42 words
A unit of the type described in claim 1 wherein said means for storing information in said memory stores information in said memory a character at a time; and including means for assembling bits received on said data bearing lines into characters.
Claim 6
Dependent Claim
93 words
A unit of the type described in claim 4 wherein said character assembling means includes a memory having a storage position for each of said lines, a register in which each received bit is stored, and a means operative each time said indicating means indicates a given line for transferring a partially assembled character from the position for the line in said memory to said register and for restoring the contents of said register to the position in said memory when said indicating means is ready to pass on to the next line.
Claim 7
Dependent Claim
53 words
A unit of the type described in claim 5 including means for detecting when a full character has been assembled in said register; and wherein said means for storing information in said memory includes means operative in response to said full-character detecting means for transferring the contents of said register into said memory.
Claim 8
Dependent Claim
49 words
A unit of the type described in claim 6 wherein at least one of said data bearing lines is a synchronous line; and including means for detecting a sync code in said register; and means responsive to said sync code detecting means for activating said full character detection means.
Claim 9
Dependent Claim
81 words
A unit of the type described in claim 4 wherein at least one of said lines is an asynchronous line; and including means for generating a clock which is related to the clock rate of said asynchronous line; means operative when a pre-determined change occurs in the condition of said asynchronous line for determining if a character is present on the line; and means responsive to said determining means for initiating the operation of said means for assembling bits into characters.
Claim 10
Dependent Claim
84 words
A unit of the type described in claim 5 including output buffer memory means having at least one position for each of said lines; means responsive to an instruction from said central processing unit for loading a character to be transmitted on a given line into a position corresponding to the line in said output buffer memory means; and wherein said means for assembling bits into characters includes character disassembly means for transmitting said character on said given line a bit at a time.
Claim 11
Dependent Claim
109 words
A unit of the type described in claim 9 wherein said character disassembly means includes a memory having a character position for each of said lines, a register, means for transferring a character to be transmitted from said output buffer memory means to the corresponding position in said disassembly means memory, means operative each time said line indicating means indicates the line for transferring the character from the disassembly means memory to the disassembly means register, and means operative when the character is in said disassembly means register and said line is available to receive a bit for transferring a bit from the disassembly means register to said line.
Claim 12
Dependent Claim
50 words
A unit of the type described in claim 1 including an interface device for at least one of said lines, said interface device having a means for assembling a character; and means operative when a character has been assembled in said interface device for transferring the character to said unit.
Claim 13
Dependent Claim
47 words
A unit of the type described in claim 11 wherein there may be a plurality of lines serviced by said interface device; and wherein said data bearing line indicating means includes means for indicating the particular one of said plurality of lines serviced by said interface device.
Claim 14
Dependent Claim
30 words
A unit of the type described in claim 1 wherein said information storing means includes means for storing an indication of the daTa bearing line being scanned with said information.
Claim 15
Dependent Claim
61 words
A unit of the type described in claim 4 including memory means for storing a control word for each of said lines; register means for storing the control word for a line each time the line is scanned; and means responsive to the control word stored in said register means for controlling the character assembly and other operations of said unit.
Claim 16
Dependent Claim
30 words
A unit of the type described in claim 14 including means for altering the control word in said register means in response to controlling means or said CPU, said unit.
Claim 17
Dependent Claim
176 words
An interface unit for a CPU, said unit comprising: means for scanning a plurality of lines; means for indicating the line being scanned at any given time; means operative when a bit is detected on a scanned line for storing the bit; means for assembling the stored bits for each line into characters; means operative when a complete character has been assembled for a given line for indicating a priority level for the line; a memory having an area for each priority level; first means responsive to said priority level indicating means for storing the complete character in said memory in the area for the indicated priority level; second means responsive to said priority level indicating means for indicating to the CPU that the unit has a character at the indicated priority level, the CPU being adapted to generate a request for a character; and means responsive to a request for a character from the CPU for transferring to the CPU a character from the highest priority area of said memory having a character to transmit.
Claim 18
Dependent Claim
176 words
An interface unit for a CPU, said unit comprising: means for scanning a plurality of lines; means for indicating the line being scanned at any given time; means operative when a bit is detected on a scanned line for storing the bit; means for assembling the stored bits for each line into characters; means operative when a complete character has been assembled for a given line for indicating a priority level for the line; a memory having an area for each priority level; first means responsive to said priority level indicating means for storing the complete character in said memory in the area for the indicated priority level; second means responsive to said priority level indicating means for indicating to the CPU that the unit has a character at the indicated priority level, the CPU being adapted to generate a request for a character; and means responsive to a request for a character from the CPU for transferring to the CPU a character from the highest priority area of said memory having a character to transmit.
Claim 19
Dependent Claim
74 words
A unit of the type described in claim 16 including means operative when a character is transferred to said CPU for determining if there are any additional characters to be transmitted from said highest priority area of memory; and means responsive to a determination that there are no further characters to be transmitted in said highest priority area for resetting the priority level indicating means for the priority level from which characters were transmitted.
Claim 20
Dependent Claim
51 words
A unit of the type described in claim 16 wherein said memory is an addressable memory; and wherein said means for storing the character in said memory includes means for indicating the address in said memory, for each of said priority levels, at which the next character is to be stored.
Claim 21
Dependent Claim
46 words
A unit of the type described in claim 16 wherein said memory is an addressable memory; and wherein said means for transferring a character to the CPU includes means for indicating, for each priority level, the address from which the next character is to be transferred.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-11 | 1978-05-13 | 1978-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-11 | 1982-05-13 | 1982-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-11 | 1986-05-13 | 1986-11-12 | $7700.00 | Window Closed / Lapsed |