Priority tabling and processing of interrupts

Claim 3

The method of claim 1 including the further steps of: a. individually storing the address of the latest data stored in each of said tables, b. individually storing the address where the latest data is to be retrieved from each of said tables, c. comparing corresponding ones of said addresses of the latest stored data and the latest data to be retrieved for corresponding tables to indicate each table that has data stored therein, d. receiving a readout signal, and E. gating the latest stored data out of the highest priority table having data stored therein upon receiving said readout signal.

Claim 4

A circuit for tabling and processing data associated with interrupt signals comprising: a. an input priority circuit for receiving a plurality of input signals having different levels of priority and selecting the one of said input signals having the highest priority, b. a like plurality of storage tables, each of said tables storing data associated only with a particular priority level, c. a plurality of input counters equal in number to said storage tables and representing corresponding levels of interrupt priority, each of said counters being associated with a corresponding one of said tables and containing an address of a storage location therein, d. gate means coupled to said counters, said priority circuit and said tables for gating out the address in the counter associated with the selected priority interrupt which enables data associated with said interrupt to be stored at the proper address in the table having a corresponding priority, e. a plurality of output counters equal in number to said input counters, each of said output counters being associated with a corresponding one of said tables and storing the address in a corresponding table where the latest data is to be retrieved, f. a like plurality of comparators for producing signals representing whether data is stored in each table by comparing the address of corresponding input and output counters, and g. an output priority circuit coupled to said comparators and said counters for selecting the highest order priority signal from said comparators and causing the address stored in a corresponding output counter to enable data stored at that address in the table with corresponding priority to be read out.

Claim 5

A circuit for tabling and processing data associated with interrupt signals comprising: a. an input priority circuit for receiving a plurality of input signals having different levels of priority and selecting the one of said input signals having the highest priority, b. a like plurality of storage tables, each of said tables storing data associated only with a particular priority level, c. a plurality of input counters equal in number to said storage tables and representing corresponding levels of interrupt priority, each of said counters being associated with a corresponding one of said tables and containing an address of a storage location therein, d. gate means coupled to said counters, said priority circuit and said tables for gating out the address in the counter associated with the selected priority interrupt which enables data associated with said interrupt to be stored at the proper address in the table having a corresponding priority, e. a plurality of output counters equal in number to said input counters, each of said output counters being associated with a corresponding one of said tables and storing the address in a corresponding table where the latest data is to be retrieved, f. a like plurality of comparators for producing signals representing whether data is stored in each table by comparing the address of corresponding input and output counters, and g. an output priority circuit coupled to said comparators and said counters for selecting the highest order priority signal from said comparators and causing the address stored in a corresponding output counter to enable data stored at that address in the table with corresponding priority to be read out.