Patent US5212662A successfully refreshed from Google Patents.
US5212662A
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Floating point arithmetic two cycle data flow
Assignee: International Business Machines Corp
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Filing: 1990-09-11
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Granted: 1993-05-18
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Expires: 2010-09-11
Abstract
Abstract A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.
Inventors
- 👤 Daniel Cocanougher
- 👤 Robert K. Montoye
- 👤 Myhong Nguyenphu
- 👤 Stephen L. Runyon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:01
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/5443; G06F7/483; G06F7/499; G06F7/49942; G06F7/49947
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
134 words
In a data processing circuit having a floating point arithmetic circuitry controller generating first, second and third cycles and providing control inputs to first, second and third arithmetic circuits, a method for performing floating point arithmetic operations comprising the steps of: performing a first floating point arithmetic operation on a set of operands during said first cycle in said first arithmetic circuit; performing a second floating point arithmetic operation on an operand and a first result of said first floating point arithmetic operation during said second cycle in said second arithmetic circuit; and providing, during a third cycle, a second result of the second floating point operation for a next successive first floating point operation to said first arithmetic circuit concurrently with performing a third floating point arithmetic operation in said third arithmetic circuit.
Claim 2
Dependent Claim
134 words
In a data processing circuit having a floating point arithmetic circuitry controller generating first, second and third cycles and providing control inputs to first, second and third arithmetic circuits, a method for performing floating point arithmetic operations comprising the steps of: performing a first floating point arithmetic operation on a set of operands during said first cycle in said first arithmetic circuit; performing a second floating point arithmetic operation on an operand and a first result of said first floating point arithmetic operation during said second cycle in said second arithmetic circuit; and providing, during a third cycle, a second result of the second floating point operation for a next successive first floating point operation to said first arithmetic circuit concurrently with performing a third floating point arithmetic operation in said third arithmetic circuit.
Claim 3
Dependent Claim
17 words
A method according to claim 1 wherein said first floating point arithmetic operation is a multiply operation.
Claim 4
Dependent Claim
16 words
A method to claim 2 wherein said second floating point arithmetic operation is an add operation.
Claim 5
Dependent Claim
30 words
A method according to claim 1 further including the step of providing a round signal during a next successive first floating point arithmetic operation if a round operation has occurred.
Claim 6
Dependent Claim
169 words
In a data processing system having a memory and a plurality of floating point arithmetic circuits, a method for performing two floating point arithmetic operations in a pipeline comprising the steps of: storing a plurality of floating point operands in said memory; performing a first floating point arithmetic operation on first and second stored operands from said memory in a first floating point circuit; performing a second floating point arithmetic operation on a third operand from said memory and a first result of the first floating point operation form said first floating point circuit in a second floating point circuit; rounding a second result of the second floating point operation from said second floating point circuit in a third floating point circuit; and determining when the second result is in a next successive first or second floating point operation and providing said second result to either the first floating point circuit or the second floating point arithmetic circuit while rounding the second result in said third floating point circuit.
Claim 7
Dependent Claim
169 words
In a data processing system having a memory and a plurality of floating point arithmetic circuits, a method for performing two floating point arithmetic operations in a pipeline comprising the steps of: storing a plurality of floating point operands in said memory; performing a first floating point arithmetic operation on first and second stored operands from said memory in a first floating point circuit; performing a second floating point arithmetic operation on a third operand from said memory and a first result of the first floating point operation form said first floating point circuit in a second floating point circuit; rounding a second result of the second floating point operation from said second floating point circuit in a third floating point circuit; and determining when the second result is in a next successive first or second floating point operation and providing said second result to either the first floating point circuit or the second floating point arithmetic circuit while rounding the second result in said third floating point circuit.
Claim 8
Dependent Claim
17 words
A method according to claim 5 wherein said first floating point arithmetic operation is a multiply operation.
Claim 9
Dependent Claim
17 words
An method according to claim 6 wherein said second floating point arithmetic operation is an add operation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-17 | 1996-11-16 | 1997-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-17 | 2000-11-16 | 2001-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-17 | 2004-11-16 | 2005-05-18 | $7700.00 | Window Closed / Lapsed |