Digital computer utilizing a plurality of parallel asynchronous arithmetic units

Claim 2

A digital computer comprising a control unit, an arithmetic unit, and an information storage unit; said information storage unit being adapted to store data and instructions in digital form; said control unit comprising means for converting instructions received from said storage unit in digital form into operating potentials; said arithmetic unit comprising a first part for performing arithmetic operations upon instructions from said storage unit in digital form and a second part for performing arithmetic operations upon data in digital form; said data arithmetic unit comprising a fraction part and an exponent part for carrying out arithmetic operations upon fractional part and the exponent part of data words simultaneously; said fraction part of said data arithmetic unit comprising a cascaded array of arithmetic processors; said array including means for applying information thereto and means for receiving information therefrom, a product generator, said product generator having at least two inputs and two outputs, and means for supplying information in digital form to both of said inputs.

Claim 3

The digital computer defined in claim 1 wherein said array receives digital data in words having a prescribed number of digits and no assigned radix point position in any word and further includes means for determining the number of zeros in a digital data word which precede the most significant non-zero digit, and left shift means for shifting said digital data word the number of places to the left which are equal to the number of zeros which precede the most significant non-zero digit in said word.

Claim 4

The digital computer defined in claim 1 wherein said array further includes accumulating means for receiving and accumulating digital data supplied thereto, and means connected to the output of said accumulating means for storing the results of said accumulation.

Claim 5

The digital Computer defined in claim 1 wherein said array further includes an adder, said adder having at least two inputs and two outputs, and means for connecting at least one input of said adder to at least one output of said product generator.

Claim 6

The digital computer defined in claim 4 wherein said array further includes first shift means for shifting digital data to the right a prescribed number of places, and further including means for indicating to said first shift means the number of places said digital data is to be shifted.

Claim 7

The digital computer defined in claim 5 further including second shift means for shifting said digital data to the right a fixed number of places when energized, and means for connecting said first and second shift means in cascade.

Claim 8

The digital computer defined in claim 6 wherein said array further includes accumulating means for receiving and accumulating digital data supplied thereto, and means connected to the output of said accumulating means for storing the results of said accumulation.

Claim 9

The digital computer defined in claim 6 wherein said array receives digital data in words having a prescribed number of digits and no assigned radix point position in any word and further includes means for determining the number of zeros in a digital data word which precede the most significant non-zero digit, and third shift means for shifting said digital data word to the left the number of places which are equal to the number of zeros which precede the most significant non-zero digit in said word.

Claim 10

The digital computer defined in claim 8 wherein said array further includes accumulating means for receiving and accumulating digital data supplied thereto, and means connected to the output of said accumulating means for storing the results of said accumulation.

Claim 11

A digital computer comprising a control unit, an arithmetic unit, and an information storage unit, said information storage unit being adapted to store data and instructions in digital form, said control unit comprising means for converting instructions received from said storage unit in digital form into operating potentials, said arithmetic unit comprising a first part for performing arithmetic operations upon instructions from said storage unit in digital form and a second part for performing arithmetic operations upon data from said storage unit in digital form, said data arithmetic unit comprising a fraction part and an exponent part for carrying out arithmetic operations upon the fractional part and the exponent part of data words simultaneously, said exponent part of said arithmetic unit comprising an adder means, said adder means having at least two inputs and two outputs, a first input channel connected to one of said adder inputs, a second channel connected to the other of said adder inputs, means for applying digital information to each of said input channels, a first register for receiving exponent information in digital form from an external source, means for connecting said first register to said first channel means for connecting, a second register to one of said outputs from said adder means, means for applying the output from said second register to the second channel, and means for complementing the output from said second register.

Claim 12

A digital computer comprising a control unit, an arithmetic unit, and an information storage unit, said information storage unit being adapted to store data and instructions in digital form, said control unit comprising means for converting instructions received from said storage unit in digital form into operating potentials, said arithmetic unit comprising a first part for performing arithmetic operations upon instructions from said storage unit in digital form and a second part for performing arithmetic operations upon data from said storage unit in digital form, said data arithmetic unit comprising a fraction part and an exponent part for carrying out arithmetic operations upon the fractional part and the exponent part of data words simultaneously, said exponent part of said arithmetic unit comprising an adder means, said adder means having at least two inputs and two outputs, a first input channel connected to one of said adder inputs, a second channel connected to the other of said adder inputs, means for applying digital information to each of said input channels, a first register for receiving exponent information in digital form from an external source, means for connecting said first register to said first channel means for connecting, a second register to one of said outputs from said adder means, means for applying the output from said second register to the second channel, and means for complementing the output from said second register.

Claim 13

The digital computer defined in claim 10 wherein said exponent arithmetic unit further includes means for connecting said other output from said adder to an input of said adder to form a ring-around carry path.

Claim 14

A digital computer comprising a first, a second, and a third arithmetic unit, said first arithmetic unit comprising an adder, said adder having at least two inputs and a single output, a first information channel connected to one of said adder inputs and a second information channel connected to the other of said adder inputs, at least a first register having its input connected to the output of said adder and its output connected to said first channel, at least a second register having its input connected to the output of saId adder and its output connected to said second channel, said first arithmetic unit further comprising means for receiving digital information from an external source, means for coupling said information to said first channel, and means for coupling said receiving means to the output of said adder.

Claim 15

A digital computer comprising a first, a second, and a third arithmetic unit, said first arithmetic unit comprising an adder, said adder having at least two inputs and a single output, a first information channel connected to one of said adder inputs and a second information channel connected to the other of said adder inputs, at least a first register having its input connected to the output of said adder and its output connected to said first channel, at least a second register having its input connected to the output of saId adder and its output connected to said second channel, said first arithmetic unit further comprising means for receiving digital information from an external source, means for coupling said information to said first channel, and means for coupling said receiving means to the output of said adder.

Claim 16

The digital computer defined in claim 12 wherein said first arithmetic unit further includes a third register, means for connecting the input of said third register to the output of said adder and means for connecting the output of said third register to both of said first and second channels.

Claim 17

The digital computer defined in claim 13 wherein said first arithmetic unit further includes means for controlling the flow of information through said first and second channels and said means connecting the inputs and the outputs to said first, second and third registers and said adder.

Claim 18

A digital computer comprising a first, a second, and a third arithmetic unit, said second arithmetic unit comprising a plurality of arithmetic components connected in cascade to form a channel through which information flows, said arithmetic components individually selectively modifying the information passing through the particular component, said plurality of arithmetic components including a product generator, said product generator having two information inputs and an information output, means for connecting said output to an input of another arithmetic component, means for connecting one of said information inputs of said product generator in said information channel, and means for connecting the other information input of said product generator to a source of digital information, said product generator being adapted to operate with information flowing therethrough rather than being stepped therethrough.

Claim 19

A digital computer comprising a first, a second, and a third arithmetic unit, said second arithmetic unit comprising a plurality of arithmetic components connected in cascade to form a channel through which information flows, said arithmetic components individually selectively modifying the information passing through the particular component, said plurality of arithmetic components including a product generator, said product generator having two information inputs and an information output, means for connecting said output to an input of another arithmetic component, means for connecting one of said information inputs of said product generator in said information channel, and means for connecting the other information input of said product generator to a source of digital information, said product generator being adapted to operate with information flowing therethrough rather than being stepped therethrough.

Claim 20

The digital computer defined in claim 15 wherein said plurality of arithmetic components includes an adder having two inputs and an output, means for connecting one of said adder inputs in said information channel, means for supplying digital information to said other adder input from an outside source of digital information, means for controlling the application of digital information from an outside source to said other input of said adder, and means for connecting the output from said adder in said channel, said adder being adapted to operate with information flowing therethrough rather than with information being stepped therethrough.

Claim 21

The digital computer defined in claim 16 wherein said second arithmetic unit further includes means for supplying digital information to said channel intermediate said arithmetic components.

Claim 22

The digital computer defined in claim 17 wherein said second arithmetic unit further includes additional arithmetic units connected in cascade in said information channel, register means connected to said channel for receiving information which has flowed through said arithmetic components, and means for connecting the output from said register to an input of said channel.