US4484300A
Expired / Lapsed
US
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Data processor having units carry and tens carry apparatus supporting a decimal multiply operation
Assignee: Bull HN Information Systems Inc
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Filing: 1980-12-24
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Granted: 1984-11-20
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Expires: 2000-12-24
Abstract
Abstract A data processing system executes a decimal multiply instruction by storing the product of a multiplier decimal digit and a multiplicand decimal digit in a read only memory and storing partial product decimal digits in a register. The units product decimal digit is read from the read only memory during one cycle and added to a partial product decimal digit. A resulting units carry is stored in a units carry flip-flop. The tens product decimal digit is read from the read only memory during another cycle and added to a higher order partial product decimal digit. A resulting tens carry is stored in a tens carry flip-flop. A multiplexer selects the output of the units carry flip-flop for adding the units carry during the next units cycle in which the next units product decimal digit is added to the higher order partial product decimal digit. The multiplexer selects the output of the tens carry flip-flop for adding the tens carry during the next tens cycle in which the next tens product decimal digit is added to a next higher order partial product decimal digit.
Inventors
- 👤 Virendra S. Negi
- 👤 Steven A. Tague
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:02
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/491; G06F7/4915
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
526 words
Apparatus for generating a carry during the execution of a decimal multiply instruction wherein a decimal digit multiplier is multiplied by a decimal digit multiplicand comprising: first means responsive to a multiplier decimal digit and a first and subsequent multiplicand decimal digits for generating a first and subsequent units product decimal digits during a first and subsequent odd cycles of operation and a first tens product decimal digit during a second and subsequent even cycles of operation; second means for storing partial product decimal digits; adder means coupled to said first and second means and responsive during said first cycle of operation to said first units product decimal digit and a first of said partial product decimal digits for generating a first units sum decimal digit for replacing said first partial product decimal digit in said second means and a carry signal in a first state indicative of a units carry or said carry signal in a second state indicative of no units carry, and responsive during said second cycle of operation to said first tens product decimal digit and a second of said partial product decimal digits for generating a first tens sum decimal digit for replacing said second partial product decimal digit in said second means and said carry signal in said first state indicative of a tens carry or said carry signal in said second state indicative of no tens carry; units carry means coupled to said adder means for storing said carry signal in said first state during said first cycle of operation; tens carry means coupled to said adder means for storing said carry signal in said first state during said second cycle of operation; multiplexer means coupled to said units and said tens carry means for receiving said carry signal in said first state during a third cycle of operation from said units carry means, and receiving said carry signal in said second state during a fourth cycle of operation; said first means responsive to said multiplier decimal digits and a second multiplicand decimal digit for generating a second units product decimal digit during said third cycle of operation and a second tens product decimal digit during said fourth cycle of operation; said adder means being further coupled to said multiplexer means for receiving, during said third cycle of operation, said carry signal in said first state, said second units product decimal digit, and said second partial product decimal digit for generating a second units sum decimal digit for replacing said second partial product decimal digit in said second means, and receiving, during said fourth cycle of operation, said carry signal in said second state, said second tens product decimal digit and a third partial product decimal digit for generating a second tens sum decimal digit for replacing said third partial product decimal digit in said second means; wherein said first multiplicand decimal digit is the least significant decimal digit and said second multiplicand decimal digit is representative of the next higher and subsequent higher order decimal digits, and said multiplier decimal digit is representative of the multiplier decimal digits with the exception of the least significant multiplier decimal digit.
Claim 2
Dependent Claim
526 words
Apparatus for generating a carry during the execution of a decimal multiply instruction wherein a decimal digit multiplier is multiplied by a decimal digit multiplicand comprising: first means responsive to a multiplier decimal digit and a first and subsequent multiplicand decimal digits for generating a first and subsequent units product decimal digits during a first and subsequent odd cycles of operation and a first tens product decimal digit during a second and subsequent even cycles of operation; second means for storing partial product decimal digits; adder means coupled to said first and second means and responsive during said first cycle of operation to said first units product decimal digit and a first of said partial product decimal digits for generating a first units sum decimal digit for replacing said first partial product decimal digit in said second means and a carry signal in a first state indicative of a units carry or said carry signal in a second state indicative of no units carry, and responsive during said second cycle of operation to said first tens product decimal digit and a second of said partial product decimal digits for generating a first tens sum decimal digit for replacing said second partial product decimal digit in said second means and said carry signal in said first state indicative of a tens carry or said carry signal in said second state indicative of no tens carry; units carry means coupled to said adder means for storing said carry signal in said first state during said first cycle of operation; tens carry means coupled to said adder means for storing said carry signal in said first state during said second cycle of operation; multiplexer means coupled to said units and said tens carry means for receiving said carry signal in said first state during a third cycle of operation from said units carry means, and receiving said carry signal in said second state during a fourth cycle of operation; said first means responsive to said multiplier decimal digits and a second multiplicand decimal digit for generating a second units product decimal digit during said third cycle of operation and a second tens product decimal digit during said fourth cycle of operation; said adder means being further coupled to said multiplexer means for receiving, during said third cycle of operation, said carry signal in said first state, said second units product decimal digit, and said second partial product decimal digit for generating a second units sum decimal digit for replacing said second partial product decimal digit in said second means, and receiving, during said fourth cycle of operation, said carry signal in said second state, said second tens product decimal digit and a third partial product decimal digit for generating a second tens sum decimal digit for replacing said third partial product decimal digit in said second means; wherein said first multiplicand decimal digit is the least significant decimal digit and said second multiplicand decimal digit is representative of the next higher and subsequent higher order decimal digits, and said multiplier decimal digit is representative of the multiplier decimal digits with the exception of the least significant multiplier decimal digit.
Claim 3
Dependent Claim
65 words
The apparatus of claim 1 wherein said units carry means comprises: a first flip-flop being responsive during said first, said third and said subsequent odd numbered cycles of operation, to said carry signal in said first state for setting, and responsive to said carry signal in said second state for resetting, if said first flip-flop was set during the previous odd numbered cycle of operation.
Claim 4
Dependent Claim
68 words
The apparatus of claim 2 wherein said tens carry means comprises: a second flip-flop being responsive, during said second, said fourth and said subsequent even numbered cycles of operation, to said carry signal in said first state for setting, and responsive to said carry signal in said second state for resetting said second flip-flop if said second flip-flop was set during the previous even numbered cycle of operation.
Claim 5
Dependent Claim
113 words
The apparatus of claim 3 wherein said multiplexer means comprises: a multiplexer coupled to said first and said second flip-flops for transferring said carry signals from said first flip-flop to said adder means during said odd numbered cycles of operation and transferring said carry signal from said second flip-flop to said adder means during said even numbered cycles of operation, said adder means adding a units carry in developing the units sum decimal digits during said odd numbered cycles of operation in which said carry signal is in said first state, and said adder means adding a tens carry in developing the tens sum decimal digits during said even numbered cycles of operation.
Claim 6
Dependent Claim
94 words
The apparatus of claim 4 further comprising: control means responsive to a predetermined configuration of control signals and coupled to said first means, said units and tens carry means, and said multiplexer means and generating a multiply tens signal in a first state indicative of said odd numbered cycles of operation and said multiply tens signal in a second state indicative of said even numbered cycles of operation, said control means further generating a units carry clear signal for resetting said first flip-flop and a tens carry clear signal for resetting said second flip-flop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-20 | 1988-05-21 | 1988-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-20 | 1992-05-21 | 1992-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-20 | 1996-05-21 | 1996-11-20 | $7700.00 | Window Closed / Lapsed |