Floating point accumulator circuit

Claim 2

A pipelined architecture, floating point number accumulator circuit for totalling a multiplicity of floating point numbers, such numbers comprising a sign, an exponent, and a mantissa, the circuit including: a. an input circuit for receiving and temporarily storing an input floating point number; b. an intermediate register for temporarily storing data; c. an exponent comparison circuit, coupled to the output of the input circuit and of the intermediate register, for determining a shift code as a function of the difference between the values of the exponent of the input number and the exponent of a numeric result previously stored in the intermediate register, and for temporarily storing the larger exponent and the shift code in the intermediate register; d. an accumulator register for temporarily accumulating non-normalized numeric results; e. an accumulation circuit, coupled to the output of the exponent comparison circuit and of the accumulator register, for shifting the mantissa of the smaller of the input number and a non-normalized numeric result, previously accumulated in the accumulator register, by the amount of the shift code to align the binary points of both numbers, and for summing the two aligned numbers as a non-normalized numeric result and accumulating the non-normalized numeric result in the accumulator register; f. a normalization circuit, coupled to the accumulator register, for converting the non-normalized numeric result of the accumulation circuit into normalized floating point number form; and g. an output circuit, coupled to the output of the normalization circuit, for temporarily storing the normalized result in an output register and for outputting the normalized result from the circuit.

Claim 3

The floating point accumulator circuit of claim 1, further including a conditional twos' complement circuit, coupled to the output of the input circuit, for calculating the twos' complement of the mantissa of the input number if the input number is negative.

Claim 4

The floating point accumulator circuit of claim 2, wherein the normalization circuit includes means for converting the non-normalized numeric result of the accumulator register into normalized form comprising: a. a conditional complement circuit for calculating the complement of the mantissa of the numeric result if the result is negative; b. circuit means for shifting the mantissa of the result until all leading zero bits are removed; and c. exponent adjustment means for adjusting the exponent of the numeric result by the amount of the zero-removal shift.

Claim 5

The floating point accumulator circuit of claim 1, wherein the normalization circuit includes means for converting the non-normalized numeric result into normalized form comprising: a. circuit means for shifting the mantissa of the result until all leading zero bits are removed; and b. exponent adjustment means for adjusting the exponent of the numeric result by the amount of the zero-removal shift.

Claim 6

The floating point accumulator circuit of claim 1, wherein the input circuit further includes circuit means for receiving portions of the input number in a time-multiplexed sequence.

Claim 7

The floating point accumulator circuit of claim 1, wherein the exponent comparison circuit further includes circuit means for adjusting the shift code if the sum from the accumulation circuit overflows.

Claim 8

A pipelined architecture, floating point number accumulator circuit for totalling a multiplicity of floating point numbers, such numbers comprising a sign, an exponent, and a mantissa, the circuit including: a. an input circuit for receiving and temporarily storing an input floating point number; b. an intermediate register for temporarily storing data; c. an exponent comparison and twos' complement circuit, coupled to the output of the input circuit and of the intermediate register, for determining a shift code as a function of the difference between the values of the exponent of the input number and the exponent of a numeric result previously stored in the intermediate register, for transforming the mantissa of the input number into the twos' complement of the input mantissa if the input number is negative, and for temporarily storing the mantissa, the larger exponent and the shift code in the intermediate register; d. an accumulator register for temporarily accumulating non-normalized numeric results; e. an accumulation circuit, coupled to the output of the exponent comparison circuit and of the accumulator register, for shifting the mantissa of the smaller of the input number and a non-normalized numeric result, previously accumulated in the accumulator register, by the amount of the shift code to align the binary points of both numbers, and for summing the two aligned numbers as a non-normalized numeric result and accumulating the non-normalized numeric result in the accumulator register; f. a normalization circuit, coupled to the accumulator register, for converting the non-normalized numeric result of the accumulation circuit into normalized floating point number form, comprising a conditional complement circuit for calculating the complement of the mantissa of the non-normalized numeric result if the result is negative, circuit means for shifting the mantissa of the non-normalized numeric result until all leading zero bits are removed, and exponent adjustment means for adjusting the exponent of the non-normalized numeric result by the amount of the zero-removal shift; and g. an output circuit, coupled to the output of the normalization circuit, for temporarily storing the normalized result in an output register and for outputting the normalized result from the circuit.

Claim 9

A pipelined architecture, floating point number accumulator circuit for totalling a multiplicity of floating point numbers, such numbers comprising a sign, an exponent, and a mantissa, the circuit including: a. an input circuit for receiving and temporarily storing an input floating point number; b. an intermediate register for temporarily storing data; c. an exponent comparison and twos' complement circuit, coupled to the output of the input circuit and of the intermediate register, for determining a shift code as a function of the difference between the values of the exponent of the input number and the exponent of a numeric result previously stored in the intermediate register, for transforming the mantissa of the input number into the twos' complement of the input mantissa if the input number is negative, and for temporarily storing the mantissa, the larger exponent and the shift code in the intermediate register; d. an accumulator register for temporarily accumulating non-normalized numeric results; e. an accumulation circuit, coupled to the output of the exponent comparison circuit and of the accumulator register, for shifting the mantissa of the smaller of the input number and a non-normalized numeric result, previously accumulated in the accumulator register, by the amount of the shift code to align the binary points of both numbers, and for summing the two aligned numbers as a non-normalized numeric result and accumulating the non-normalized numeric result in the accumulator register; f. a normalization circuit, coupled to the accumulator register, for converting the non-normalized numeric result of the accumulation circuit into normalized floating point number form, comprising a conditional complement circuit for calculating the complement of the mantissa of the non-normalized numeric result if the result is negative, circuit means for shifting the mantissa of the non-normalized numeric result until all leading zero bits are removed, and exponent adjustment means for adjusting the exponent of the non-normalized numeric result by the amount of the zero-removal shift; and g. an output circuit, coupled to the output of the normalization circuit, for temporarily storing the normalized result in an output register and for outputting the normalized result from the circuit.

Claim 10

The floating point accumulator circuit of claim 7, wherein the input circuit further includes circuit means for receiving portions of the input number in a time-multiplexed sequence.

Claim 11

The floating point accumulator circuit of claim 7, wherein the exponent comparison circuit further includes circuit means for adjusting the shift code if the sum from the accumulation circuit overflows.

Claim 12

A floating point number accumulator circuit for totalling a multiplicity of floating point numbers, such numbers comprising a sign, and exponent, and a mantissa, the circuit including: a. an input circuit for receiving an input floating point number; b. an exponent comparison circuit, coupled to the output of the input circuit and to an accumulation circuit, for determining a shift code as a function of the larger of the exponent of the input number and the exponent of a numeric result previously accumulated in the accumulation circuit; c. wherein the accumulation circuit is coupled to the output of the exponent comparison circuit and includes an accumulator register, the accumulation circuit further including means for shifting the mantissa of the smaller of the input number and a non-normalized numeric result, previously accumulated in the accumulator register, by the amount of the shift code to align the binary points of both numbers, and for summing the two aligned numbers as a non-normalized numeric result and accumulating the non-normalized numeric result in the accumulator register; d. a normalization circuit, coupled to the accumulator register, for converting the non-normalized numeric result of the accumulation register into normalized floating point number form; and e. an output circuit, coupled to the output of the normalization circuit, for outputting the normalized result from the circuit.

Claim 13

A floating point number accumulator circuit for totalling a multiplicity of floating point numbers, such numbers comprising a sign, and exponent, and a mantissa, the circuit including: a. an input circuit for receiving an input floating point number; b. an exponent comparison circuit, coupled to the output of the input circuit and to an accumulation circuit, for determining a shift code as a function of the larger of the exponent of the input number and the exponent of a numeric result previously accumulated in the accumulation circuit; c. wherein the accumulation circuit is coupled to the output of the exponent comparison circuit and includes an accumulator register, the accumulation circuit further including means for shifting the mantissa of the smaller of the input number and a non-normalized numeric result, previously accumulated in the accumulator register, by the amount of the shift code to align the binary points of both numbers, and for summing the two aligned numbers as a non-normalized numeric result and accumulating the non-normalized numeric result in the accumulator register; d. a normalization circuit, coupled to the accumulator register, for converting the non-normalized numeric result of the accumulation register into normalized floating point number form; and e. an output circuit, coupled to the output of the normalization circuit, for outputting the normalized result from the circuit.