Noncacheable address random access memory

Claim 2

A computer system, comprising: a processor having a plurality of address lines for requesting stored information; cache memory for storing information and coupled to said address lines; a cache memory controller coupled to said address lines to determine if said requested stored information is stored in said cache memory and having a noncacheable address input for receiving a signal indicating whether said requested information is cacheable; random access memory not forming a portion of said cache controller and having a plurality of address inputs, a write enable input, a data input and a data output for storing data values representing the cacheable status of a memory block, said address inputs of sad random access memory coupled to said address lines for addressing said data values and said data output of said random access memory coupled to said noncacheable address input; means for indicating a write request of said random access memory; and means for storing said cacheable status data values in said random access memory, wherein said storing means includes means for storing a value indicative of a programming mode request, means for storing said cacheable status data values prior to being stored in said random access memory and means responsive to a memory write operation, said programming mode request value and said write request indication for enabling said stored data value to said random access memory data input and for providing a value to said random access memory write enable input to allow said random access memory to store said stored data value.

Claim 3

The computer system of claim 1, wherein said storing means further includes means for clearing said programming mode request value after a memory write operation.

Claim 4

The computer system of claim 2, wherein said storing means further includes means for designating said memory write operation as a local bus operation.

Claim 5

A computer system, comprising: a processor having a plurality of address lines for requesting stored information; cache memory for storing information and coupled to said address lines; a cache memory controller coupled to said address lines to determine if said requested stored information is stored in said cache memory and having a noncacheable address input for receiving a signal indicating whether said requested information is cacheable; random access memory not forming a portion of said cache controller and having a plurality of address inputs, and a data output for storing data values representing the cacheable status of a memory block, said address inputs of said random access memory coupled to said address lines for addressing said data values and said data output of said random access memory coupled to said noncacheable address input; means for indicating a write request of said random access memory; and means for reading said cacheable status data values from said random access memory, wherein said reading means includes means for storing a value indicative of a programming mode request and means coupled to said random access memory data output for storing a data value contained in said random access memory for reading by said processor, wherein said data value storing means includes a data latching input and said reading means further includes means responsive to a memory write operation, said programming mode request value and said read request indication for providing a signal to said data value storing means to allow said data value storing means to store the data value provided by said random access memory.

Claim 6

A computer system, comprising: a processor having a plurality of address lines for requesting stored information; cache memory for storing information and coupled to said address lines; a cache memory controller coupled to said address lines to determine if said requested stored information is stored in said cache memory and having a noncacheable address input for receiving a signal indicating whether said requested information is cacheable; random access memory not forming a portion of said cache controller and having a plurality of address inputs, and a data output for storing data values representing the cacheable status of a memory block, said address inputs of said random access memory coupled to said address lines for addressing said data values and said data output of said random access memory coupled to said noncacheable address input; means for indicating a write request of said random access memory; and means for reading said cacheable status data values from said random access memory, wherein said reading means includes means for storing a value indicative of a programming mode request and means coupled to said random access memory data output for storing a data value contained in said random access memory for reading by said processor, wherein said data value storing means includes a data latching input and said reading means further includes means responsive to a memory write operation, said programming mode request value and said read request indication for providing a signal to said data value storing means to allow said data value storing means to store the data value provided by said random access memory.

Claim 7

The computer system of claim 4, wherein said reading means further includes means for clearing said programming mode request value after a memory write operation.

Claim 8

The computer system of claim 5, wherein said reading means further includes means for designating said memory write operation as a local bus operation.

Claim 9

A computer system, comprising: a bus having a plurality of address lines for requesting or storing information and a plurality of data lines for transferring information; memory having address inputs coupled to said address lines and data ports coupled to said data lines; random access memory for storing memory characteristic values, said memory characteristic values signifying particular characteristics of said memory, having address inputs coupled to said address lines for addressing said characteristic values, a write enable input, a data input and a data output; means for indicating a write request of said random access memory; and means coupled to said data output of said random access memory for interpreting said characteristic values and performing the proper operation based on said interpretation; and means for storing said characteristic data values in said random access memory, wherein said storing means includes means for storing a value indicative of a programming mode request, means for storing said cacheable status data values prior to being stored in said random access memory and means responsive to a memory write operation, said programming mode request value and said write request indication for enabling said stored data value to said random access memory data input and for providing a value to said random access memory write enable input to allow said random access memory to store said stored data value.

Claim 10

A computer system, comprising: a bus having a plurality of address lines for requesting or storing information and a plurality of data lines for transferring information; memory having address inputs coupled to said address lines and data ports coupled to said data lines; random access memory for storing memory characteristic values, said memory characteristic values signifying particular characteristics of said memory, having address inputs coupled to said address lines for addressing said characteristic values, a write enable input, a data input and a data output; means for indicating a write request of said random access memory; and means coupled to said data output of said random access memory for interpreting said characteristic values and performing the proper operation based on said interpretation; and means for storing said characteristic data values in said random access memory, wherein said storing means includes means for storing a value indicative of a programming mode request, means for storing said cacheable status data values prior to being stored in said random access memory and means responsive to a memory write operation, said programming mode request value and said write request indication for enabling said stored data value to said random access memory data input and for providing a value to said random access memory write enable input to allow said random access memory to store said stored data value.

Claim 11

The computer system of claim 7, wherein said storing means further includes means for clearing said programming mode request value after a memory write operation.

Claim 12

The computer system of claim 8, wherein said storing means further includes means for designating said memory write operation as a local bus operation.

Claim 13

A computer system, comprising: a bus having a plurality of address lines for requesting or storing information and a plurality of data lines for transferring information; memory having address inputs coupled to said address lines and data ports coupled to said data lines; random access memory for storing memory characteristic values, said memory characteristic values signifying particular characteristics of said memory, having address inputs coupled to said address lines for addressing said characteristic and a data output; means for indicating a read request of said random access memory; means coupled to said data output of said random access memory for interpreting said characteristic values and performing the proper operation based on said interpretation; and means for reading said characteristic data values from said random access memory, wherein said reading means includes means for storing a value indicative of a programming mode request and means coupled to said random access memory data output for storing a data output value contained in said random access memory for reading over said bus, wherein said data value storing means includes a data latching input and said reading means further includes means responsive to a memory write operation, said programming mode request value and said read request indication for providing a signal to said data value storing means to store the data value provided by said random access memory.

Claim 14

A computer system, comprising: a bus having a plurality of address lines for requesting or storing information and a plurality of data lines for transferring information; memory having address inputs coupled to said address lines and data ports coupled to said data lines; random access memory for storing memory characteristic values, said memory characteristic values signifying particular characteristics of said memory, having address inputs coupled to said address lines for addressing said characteristic and a data output; means for indicating a read request of said random access memory; means coupled to said data output of said random access memory for interpreting said characteristic values and performing the proper operation based on said interpretation; and means for reading said characteristic data values from said random access memory, wherein said reading means includes means for storing a value indicative of a programming mode request and means coupled to said random access memory data output for storing a data output value contained in said random access memory for reading over said bus, wherein said data value storing means includes a data latching input and said reading means further includes means responsive to a memory write operation, said programming mode request value and said read request indication for providing a signal to said data value storing means to store the data value provided by said random access memory.

Claim 15

The computer system of claim 10, wherein said reading means further includes means for clearing said programming mode request value after a memory write operation.

Claim 16

The computer system of claim 11, wherein said reading means further includes means for designating said memory write operation as a local bus operation.