Semiconductor device with input protection circuit of high withstand voltage

Claim 2

An input protection circuit for a semiconductor device using a FET, comprising: a semiconductor substrate; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a gate insulation film provided on the semiconductor substrate corresponding to a region between the source region and the drain region, having a thickness greater than that of a gate insulation film in the FET of the semiconductor device; wherein one of the source region and the drain region is connected with an external input terminal for the semiconductor device, while the gate electrode and the other one of the source region and the drain region are connected with a power source for the semiconductor device.

Claim 3

The input protection circuit of claim 1, wherein the thickness of the gate insulation film is greater than 450 Å.

Claim 4

The input protection circuit of claim 1, wherein the gate electrode and the additional gate electrode is connected together inside the gate insulation film.

Claim 5

The input protection circuit of claim 1, further comprising an extra gate electrode provided inside the gate insulation film at such a position that the thickness of the gate insulation film between the extra gate electrode and the semiconductor substrate is greater than the thickness of the gate insulation film in the FET of the semiconductor device.

Claim 6

The input protection circuit of claim 4, wherein the extra gate electrode and the additional gate electrode is connected together inside the gate insulation film.

Claim 7

The input protection circuit of claim 1, further comprising low impurity concentration diffusion layer regions provided adjacent to the source region and the drain region at portions underneath the gate insulation film corresponding to intervals between the gate electrode and each one of the source region and the drain region.

Claim 8

The input protection circuit of claim 1, wherein the source region and the drain region are formed to have a high impurity concentration.

Claim 9

The input protection circuit of claim 7, wherein the impurity concentration of the source region and the drain region is greater than 1 × 10 20 cm -3 .

Claim 10

The input protection circuit of claim 1, wherein the semiconductor substrate, source region, and drain region form a bipolar transistor configuration with the semiconductor substrate as a base region, the source region as an emitter region, and the drain region as a collector region.

Claim 11

The input protection circuit of claim 1, wherein the semiconductor device also includes a high withstand voltage FET, and the thickness of the gate insulation film is equal to that of a gate insulation film of the high withstand voltage FET of the semiconductor device.

Claim 12

The input protection circuit of claim 10, wherein the input protection circuit has a gate structure identical to that of the high withstand voltage FET.

Claim 13

A semiconductor device, comprising: a FET; and an input protection device, including: a semiconductor substrate; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a gate insulation film provided on the semiconductor substrate corresponding to a region between the source region and the drain region, having a thickness greater than that of a gate insulation film in the FET of the semiconductor device; a gate electrode provided on the gate insulation film; and an additional gate electrode provided inside the gate insulation film at such a position that the thickness of the gate insulation film between the additional gate electrode and the semiconductor substrate is greater than the thickness of the gate insulation film in the FET of the semiconductor device; wherein one of the source region and the drain region is connected with an external input terminal for the semiconductor device, while the gate electrode and the other one of the source region and the drain region are connected with a power source for the semiconductor device.

Claim 14

A semiconductor device, comprising: a FET; and an input protection device, including: a semiconductor substrate; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a gate insulation film provided on the semiconductor substrate corresponding to a region between the source region and the drain region, having a thickness greater than that of a gate insulation film in the FET of the semiconductor device; a gate electrode provided on the gate insulation film; and an additional gate electrode provided inside the gate insulation film at such a position that the thickness of the gate insulation film between the additional gate electrode and the semiconductor substrate is greater than the thickness of the gate insulation film in the FET of the semiconductor device; wherein one of the source region and the drain region is connected with an external input terminal for the semiconductor device, while the gate electrode and the other one of the source region and the drain region are connected with a power source for the semiconductor device.

Claim 15

The semiconductor device of claim 12, wherein the thickness of the gate insulation film is greater than 450 Å.

Claim 16

The semiconductor device of claim 12, wherein the gate electrode and the additional gate electrode is connected together inside the gate insulation film.

Claim 17

The semiconductor device of claim 12, further comprising an extra gate electrode provided inside the gate insulation film at such a position that the thickness of the gate insulation film between the extra gate electrode and the semiconductor substrate is greater than the thickness of the gate insulation film i the FET of the semiconductor device.

Claim 18

The semiconductor device of claim 15, wherein the extra gate electrode and the additional gate electrode is connected together inside the gate insulation film.

Claim 19

The semiconductor device of claim 12, further comprising low impurity concentration diffusion layer regions provided adjacent to the source region and the drain region at portions underneath the gate insulation film corresponding to the intervals between the gate electrode and each one of the source region and the drain region.

Claim 20

The semiconductor device of claim 12, wherein the source region and the drain region are formed to have a high impurity concentration.

Claim 21

The semiconductor device of claim 18, wherein the impurity concentration of the source region and the drain region is greater than 1 × 10 20 cm -3 .

Claim 22

The semiconductor device of claim 12, wherein the semiconductor substrate, source region, and drain region form a bipolar transistor configuration with the semiconductor substrate as a base region, the source region as an emitter region, and the drain region as a collector region.

Claim 23

The semiconductor device of claim 12, further including a high withstand voltage FET, where the thickness of the gate insulation film of the input protection circuit is equal to that of a gate insulation film of the high withstand voltage FET.

Claim 24

The semiconductor device of claim 21, wherein the input protection circuit has a gate structure identical to that of the high withstand voltage FET.