Semiconductor integrated circuit device and method of manufacturing the same

Claim 1

A semiconductor integrated circuit device comprising: a semiconductor substrate (10), a first MOSFET (12) of a first conductivity type which is formed on said semiconductor substrate (10) and which has a shource or drain region (24) comprising a first semiconductor region (27)- of high impurity concentration, and a second semiconductor region (26) having an impurity concentration lower than that of said first semiconductor region (27) and formed closer to a channel side than said first semiconductor region (27),and a second MOSFET (11) of the first conductivity type which is formed on said semiconductor substrate (10), and which has a source or drain region (18) comprising a third semiconductor region (20) having an impurity concentration higher than that of said second semiconductor region (26) and formed by a step different from those of said first and second semiconductor regions (27, 26), said source or drain region (18) of said second MOSFET (11) being connected to a bonding pad.

Claim 5

The device of any of claims 1 to 3, wherein the impurity concentration of said third semiconductor region (20) is at least 1 x 10 19 /cm 3 .

Claim 6

The device of any of claims 1 to 4, wherein said third semiconductor region (20) includes therein a region (19) which is formed by the same step as said first or said second semiconductor region (27, 26).

Claim 7

The device of any of claims 1 to 5, further comprising side wall spacers (25, 22, 30) which are formed on two side walls of each of the gate electrodes (23, 17, 28) of said first, second and third MOSFETs (12, 11, 13), wherein said first semiconductor region (27) is defined by said gate electrode (23) of said first MOSFET (12) and said side wall spacers (25), and said second semiconductor region (26) is defined by said gate electrode (23) of said first MOSFET (12).

Claim 10

A method of manufacturing a semiconductor integrated circuit device which has first and second MOSFETs (12, 11) formed on a semiconductor substrate (10), comprising: forming gate electrodes (23, 17) of said first and second MOSFETs (12, 11) on said semiconductor substrate (10), introducing an impurity of the first conductivity type at a low concentration into at least a region to form said first MOSFET (12), by employing said gate electrodes (23, 17) as a mask, whereby first semiconductor regions (19, 26) are formed, forming side wall spacers (25, 22) on two side walls of each of said gate electrodes (23, 17) of said first and second MOSFETs (12, 11), introducing an impurity of the first conductivity type into a region to form said second MOSFET (11), by employing said gate electrode (17) of said second MOSFET (11) and said side wall spacers (22) thereof as a mask, whereby second semiconductor regions (20) as source and drain regions (18) of said second MOSFET (11) are formed, the impurity concentration of said second semiconductor regions (20) being higher than that of said first semiconductor regions (19), and introducing an impurity of the first conductivity type into at least said region to form said first MOSFET (12), by employing said gate electrode (23) and said side wall spacers (25) as a mask, whereby third semiconductor regions (27) are formed, the impurity concentration of said third semiconductor regions (27) being higher than that of said first semiconductor regions (26), a source or drain region (24) of said first MOSFET (11) being made of said first and third semiconductor regions (26, 27).

Claim 11

A method of manufacturing a semiconductor integrated circuit device which has first and second MOSFETs (12, 11) formed on a semiconductor substrate (10), comprising: forming gate electrodes (23, 17) of said first and second MOSFETs (12, 11) on said semiconductor substrate (10), introducing an impurity of the first conductivity type at a low concentration into at least a region to form said first MOSFET (12), by employing said gate electrodes (23, 17) as a mask, whereby first semiconductor regions (19, 26) are formed, forming side wall spacers (25, 22) on two side walls of each of said gate electrodes (23, 17) of said first and second MOSFETs (12, 11), introducing an impurity of the first conductivity type into a region to form said second MOSFET (11), by employing said gate electrode (17) of said second MOSFET (11) and said side wall spacers (22) thereof as a mask, whereby second semiconductor regions (20) as source and drain regions (18) of said second MOSFET (11) are formed, the impurity concentration of said second semiconductor regions (20) being higher than that of said first semiconductor regions (19), and introducing an impurity of the first conductivity type into at least said region to form said first MOSFET (12), by employing said gate electrode (23) and said side wall spacers (25) as a mask, whereby third semiconductor regions (27) are formed, the impurity concentration of said third semiconductor regions (27) being higher than that of said first semiconductor regions (26), a source or drain region (24) of said first MOSFET (11) being made of said first and third semiconductor regions (26, 27).

Claim 14

A method of manufacturing a semiconductor integrated circuit device which has first and second MOSFETs (12, 11) of N-channel type and a third MOSFET (13) of P-channel type which are formed on a semiconductor substrate (10), comprising: forming gate electrodes (23, 17, 28) of said first, second and third MOSFETs (12, 11, 13) on said semiconductor substrate (10), forming on said semiconductor substrate (10) a first mask (40) which covers at least a region to form said third MOSFET (13), introducing, after forming said first mask (40), an impurity of a first conductivity type at a low concentration into at least a region to form said first MOSFET (12), by employing said gate electrodes (23, 17) as a mask, whereby first semiconductor regions (19, 26) are formed, forming side wall spacers (25, 22, 30) on two side walls of each of said gate electrodes ( 23, 27, 28) of said first, second and third MOSFETs (12, 11, 13), forming on said semiconductor substrate (10) a second mask (43) which covers regions to form said first and third MOSFETs (12, 13), introducing, after forming said second mask (43), an impurity of the first conductivity type into a region to form said second MOSFET (11), by employing said gate electrode (17) and said side wall spacers (22) as a mask, whereby second semiconductor regions (20) as source and drain regions (18) of said second MOSFET (11) are formed, the impurity concentration of said second semiconductor regions (20) being higher than that of said first semiconductor regions (19), forming on said semiconductor substrate (10) a third mask (45) which covers at least a region to form said third MOSFET (13), introducing, after forming said third mask (45), an impurity of the first conductivity type into at least said region to form said first MOSFET (12) by employing said gate electrode (23) and said side wall spacers (25) as a mask, whereby third semiconductor regions (27) are formed, the impurity concentration of said third semiconductor regions (27) being higher than that of said first semiconductor regions (26), a source or drain region (24) of said first MOSFET being made of said first and third semiconductor regions (26, 27), forming on said semiconductor substrate (10) a fourth mask (47) which covers regions to form said first and second MOSFETs (12, 11), and introducing an impurity of a second conductivity type into said region to form said third MOSFET (13), by employing said gate electrode (28) and said side wall spacers (30) as a mask, whereby fourth semiconductor regions (29) as source and drain regions of said third MOSFET (13) are formed.

Claim 15

A method of manufacturing a semiconductor integrated circuit device which has first and second MOSFETs (12, 11) of N-channel type and a third MOSFET (13) of P-channel type which are formed on a semiconductor substrate (10), comprising: forming gate electrodes (23, 17, 28) of said first, second and third MOSFETs (12, 11, 13) on said semiconductor substrate (10), forming on said semiconductor substrate (10) a first mask (40) which covers at least a region to form said third MOSFET (13), introducing, after forming said first mask (40), an impurity of a first conductivity type at a low concentration into at least a region to form said first MOSFET (12), by employing said gate electrodes (23, 17) as a mask, whereby first semiconductor regions (19, 26) are formed, forming side wall spacers (25, 22, 30) on two side walls of each of said gate electrodes ( 23, 27, 28) of said first, second and third MOSFETs (12, 11, 13), forming on said semiconductor substrate (10) a second mask (43) which covers regions to form said first and third MOSFETs (12, 13), introducing, after forming said second mask (43), an impurity of the first conductivity type into a region to form said second MOSFET (11), by employing said gate electrode (17) and said side wall spacers (22) as a mask, whereby second semiconductor regions (20) as source and drain regions (18) of said second MOSFET (11) are formed, the impurity concentration of said second semiconductor regions (20) being higher than that of said first semiconductor regions (19), forming on said semiconductor substrate (10) a third mask (45) which covers at least a region to form said third MOSFET (13), introducing, after forming said third mask (45), an impurity of the first conductivity type into at least said region to form said first MOSFET (12) by employing said gate electrode (23) and said side wall spacers (25) as a mask, whereby third semiconductor regions (27) are formed, the impurity concentration of said third semiconductor regions (27) being higher than that of said first semiconductor regions (26), a source or drain region (24) of said first MOSFET being made of said first and third semiconductor regions (26, 27), forming on said semiconductor substrate (10) a fourth mask (47) which covers regions to form said first and second MOSFETs (12, 11), and introducing an impurity of a second conductivity type into said region to form said third MOSFET (13), by employing said gate electrode (28) and said side wall spacers (30) as a mask, whereby fourth semiconductor regions (29) as source and drain regions of said third MOSFET (13) are formed.