US5208170A
Expired / Lapsed
US
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Method for fabricating bipolar and CMOS devices in integrated circuits using contact metallization for local interconnect and via landing
Assignee: International Business Machines Corp
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Filing: 1991-09-18
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Granted: 1993-05-04
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Expires: 2011-09-18
Abstract
Abstract A method for fabricating bipolar and CMOS devices in integrated circuits using W as a local interconnect and via landing pad for bipolar and CMOS devices. The method includes the forming of an oxide/silicon bilayer above a local interconnect of tungsten/titanium wherein the oxide is patterned as a mask for the silicon/tungsten/titanium reactive ion etch, and the silicon layer above the tungsten/titanium layer is used as an etch stop for a via etch. The silicon layer is then reacted and converted to titanium silicide after the via etch to provide a low resistance path in the via from the local interconnect in a self aligned manner.
Inventors
- 👤 Edward Kobeda
- 👤 Gary L. Patton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:34
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; H10P; H10P50/00; H10P50/71; H10W20/064; H10W20/066; H10W20/071; H10W20/074; H10W20/077; H10W20/093; H10W20/094
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
212 words
A method for fabricating semiconductor devices in integrated circuits including the use of contact metallization for local interconnect and via landing comprising the steps of: Step 1. depositing a layer of titanium on a semiconductor substrate having an emitter structure disposed thereon, said titanium layer overlapping said emitter structure, Step 2. depositing a layer of tungsten over said titanium layer, Step 3. depositing a layer of silicon over said tungsten layer, Step 4. depositing a first layer of silicon dioxide over said silicon layer, Step 5. patterning said titanium layer, said tungsten layer and said silicon layer, Step 6. depositing a second layer of silicon dioxide over said first layer of silicon dioxide and a portion of said semiconductor substrate, Step 7. forming a photoresist mask layer over said second silicon dioxide layer and etching said second silicon dioxide layer through said photoresist mask, Step 8. using said etched second silicon dioxide layer as a mask, reactive ion etching said second silicon dioxide layer to form a recess in said second silicon dioxide layer above said silicon layer, Step 9. depositing a titanium layer on the surfaces of said recess, said titanium forming a low resistance titanium silicide by reaction with silicon at the surface of said silicon layer under said recess.
Claim 2
Independent Claim
212 words
A method for fabricating semiconductor devices in integrated circuits including the use of contact metallization for local interconnect and via landing comprising the steps of: Step 1. depositing a layer of titanium on a semiconductor substrate having an emitter structure disposed thereon, said titanium layer overlapping said emitter structure, Step 2. depositing a layer of tungsten over said titanium layer, Step 3. depositing a layer of silicon over said tungsten layer, Step 4. depositing a first layer of silicon dioxide over said silicon layer, Step 5. patterning said titanium layer, said tungsten layer and said silicon layer, Step 6. depositing a second layer of silicon dioxide over said first layer of silicon dioxide and a portion of said semiconductor substrate, Step 7. forming a photoresist mask layer over said second silicon dioxide layer and etching said second silicon dioxide layer through said photoresist mask, Step 8. using said etched second silicon dioxide layer as a mask, reactive ion etching said second silicon dioxide layer to form a recess in said second silicon dioxide layer above said silicon layer, Step 9. depositing a titanium layer on the surfaces of said recess, said titanium forming a low resistance titanium silicide by reaction with silicon at the surface of said silicon layer under said recess.
Claim 3
Dependent Claim
91 words
A method for fabricating semiconductor structures according to claim 1 further including the steps of: Step 8. removing the unreacted portions of said titanium layer from said surfaces of said recess, Step 9. depositing a new layer of titanium on said recess surfaces and depositing a layer of titanium nitride over said new layer of titanium, Step 10. filling said recess with tungsten wherein said titanium silicide formed in Step 7 provides a low resistance interconnection between said tungsten layer deposited in Step 2 and said tungsten filled in said recess.
References Cited (Backward Citations)
US4358891A
Cited
US4398335A
Cited
US4671970A
Cited
JPS63168034A
Cited
US4884123A
Cited
US4764484A
Cited
US4948755A
Cited
US4962414A
Cited
US4994410A
Cited
US4829024A
Cited
US4992391A
Cited
US5057447A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-03 | 1996-11-02 | 1997-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-03 | 2000-11-02 | 2001-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-03 | 2004-11-02 | 2005-05-04 | $7700.00 | Window Closed / Lapsed |