Process for fabricating a control gate for a floating gate FET

Claim 2

A process for fabricating a control gate line for a floating gate field effect transistor formed in a semiconductor substrate, comprising the steps of: (a) providing a floating gate overlying the substrate; (b) providing an inter-gate oxide overlying the floating gate; (c) providing a first undoped polysilicon layer overlying the inter-gate oxide; (d) providing a silicide layer overlying the first polysilicon layer; (e) providing a second undoped polysilicon layer overlying the silicide layer; (f) doping the first and second polysilicon layers after said steps (d) and (e); and (g) etching the first polysilicon layer, the silicide layer and the second polysilicon layer to form a conductive line after said step (f).

Claim 3

A process according to claim 1, wherein said step (f) comprises annealing the first and second polysilicon layers in an environment including POCl 3 .

Claim 4

A process according to claim 1, wherein said step (f) comprises concurrently doping the first and second polysilicon layers.

Claim 5

A process according to claim 1, wherein said step (f) comprises providing the first and second polysilicon layers with a doping concentration of at least approximately 5×10 19 cm -3 .

Claim 6

A process according to claim 1, wherein said step (f) comprises providing the first and second polysilicon layers with a doping concentration of greater than approximately 1×10 20 cm -3 .

Claim 7

A process according to claim 1, wherein said step (f) comprises providing the first and second polysilicon layers with a doping concentration of approximately 3-5×10 20 cm -3 .

Claim 8

A process for fabricating a field-effect transistor, comprising the sequential steps of: (a) providing a gate oxide on the substrate; (b) providing a floating gate line on the gate oxide; (c) providing an intergate oxide layer overlying the gate oxide and the floating gate line; (d) providing control gate layers, including a first undoped polysilicon layer overlying the intergate oxide layer, a silicide layer overlying the first polysilicon layer, and a second undoped polysilicon layer overlying the silicide layer; (e) annealing the control gate layers in an environment including ROCl 3 ; (f) providing a capping oxide layer overlying the control gate layers; (g) etching the control gate layers to form a control gate line; (h) etching the floating gate line using the capping oxide layer and the control gate line as a mask to form a floating gate; and (i) implanting source and drain regions using the control gate line as a mask.

Claim 9

A process for fabricating a field-effect transistor, comprising the sequential steps of: (a) providing a gate oxide on the substrate; (b) providing a floating gate line on the gate oxide; (c) providing an intergate oxide layer overlying the gate oxide and the floating gate line; (d) providing control gate layers, including a first undoped polysilicon layer overlying the intergate oxide layer, a silicide layer overlying the first polysilicon layer, and a second undoped polysilicon layer overlying the silicide layer; (e) annealing the control gate layers in an environment including ROCl 3 ; (f) providing a capping oxide layer overlying the control gate layers; (g) etching the control gate layers to form a control gate line; (h) etching the floating gate line using the capping oxide layer and the control gate line as a mask to form a floating gate; and (i) implanting source and drain regions using the control gate line as a mask.

Claim 10

A process according to claim 7, wherein said step (e) comprises providing the first and second polysilicon layers with a doping concentration of at least 5×10 20 cm -3 .

Claim 11

A process according to claim 7, wherein said step (e) comprises providing the first and second polysilicon layers with a doping concentration of greater than approximately 1×10 20 cm -3 .

Claim 12

A process according to claim 7, wherein said step (e) comprises providing the first and second polysilicon layers with a doping concentration of approximately 3-5×10 230 cm -3 .

Claim 13

A process for fabricating an integrated circuit having a plurality of transistors including at least one floating gate field-effect transistor formed in a substrate, comprising of the steps of: (a) providing a gate oxide on the substrate; (b) providing floating gate lines on the gate oxide; (c) providing an intergate oxide layer overlying the gate oxide and the floating gate lines; (d) removing selected portions of the gate oxide and the intergate oxide corresponding to the positions of buried contacts; (e) providing control gate layers, including a first undoped polysilicon layer overlying the intergate oxide layer and and contacting the substrate in the regions where the gate oxide and intergate oxide are remove,, a silicide layer overlying the first polysilicon layer, and a second undoped polysilicon layer overlying the silicide layer; (f) annealing the control gate layers in an environment including POCl 3 ; (g) thermally oxidizing the second polysilicon layer to form a capping oxide; (h) etching the capping oxide and the control gate layers to form control gate lines and buried contacts; (i) etching the floating gate lines using the capping oxide and the control gate line as a mask to form floating gates underlying the control gate lines; and (j) implanting source and drain regions using the capping oxide and the control gate lines as masks.

Claim 14

A process for fabricating an integrated circuit having a plurality of transistors including at least one floating gate field-effect transistor formed in a substrate, comprising of the steps of: (a) providing a gate oxide on the substrate; (b) providing floating gate lines on the gate oxide; (c) providing an intergate oxide layer overlying the gate oxide and the floating gate lines; (d) removing selected portions of the gate oxide and the intergate oxide corresponding to the positions of buried contacts; (e) providing control gate layers, including a first undoped polysilicon layer overlying the intergate oxide layer and and contacting the substrate in the regions where the gate oxide and intergate oxide are remove,, a silicide layer overlying the first polysilicon layer, and a second undoped polysilicon layer overlying the silicide layer; (f) annealing the control gate layers in an environment including POCl 3 ; (g) thermally oxidizing the second polysilicon layer to form a capping oxide; (h) etching the capping oxide and the control gate layers to form control gate lines and buried contacts; (i) etching the floating gate lines using the capping oxide and the control gate line as a mask to form floating gates underlying the control gate lines; and (j) implanting source and drain regions using the capping oxide and the control gate lines as masks.

Claim 15

A process for fabricating a floating gate field-effect transistor (FET) on a substrate, comprising the sequential steps of: (a) providing a gate oxide overlying the substrate; (b) providing a first polysilicon layer overlying the gate oxide layer; (c) annealing the first polysilicon layer in an environment including POCl 3 ; (d) etching the first polysilicon layer to form floating gate lines; (e) providing an inter-gate oxide layer overlying the floating gate lines and the gate oxide; (f) placing the substrate in a vacuum chamber and reducing the pressure in the vacuum chamber; (g) providing control gate material layers overlying the intergate oxide layer, the control gate material layers including a second undoped polysilicon layer, a silicide layer overlying the second polysilicon layer and a third undoped polysilicon layer overlying the silicide layer, without breaking the vacuum formed in said step (f); (h) annealing the substrate in an environment including POCl 3 to provide the second and third polysilicon layers with a doping concentration greater than approximately 1×10 20 cm -3 ; (i) thermally oxidizing the third polysilicon layer to form a capping oxide layer; (j) etching the capping oxide layer, the control gate material layers, and the inter-gate oxide layer to form control gate lines; (k) etching the floating gate lines using the capping oxide and the control gate lines as masks to form floating gates; and (l) implanting source and drain regions using the control gate lines as masks.

Claim 16

A process for fabricating a floating gate field-effect transistor (FET) on a substrate, comprising the sequential steps of: (a) providing a gate oxide overlying the substrate; (b) providing a first polysilicon layer overlying the gate oxide layer; (c) annealing the first polysilicon layer in an environment including POCl 3 ; (d) etching the first polysilicon layer to form floating gate lines; (e) providing an inter-gate oxide layer overlying the floating gate lines and the gate oxide; (f) placing the substrate in a vacuum chamber and reducing the pressure in the vacuum chamber; (g) providing control gate material layers overlying the intergate oxide layer, the control gate material layers including a second undoped polysilicon layer, a silicide layer overlying the second polysilicon layer and a third undoped polysilicon layer overlying the silicide layer, without breaking the vacuum formed in said step (f); (h) annealing the substrate in an environment including POCl 3 to provide the second and third polysilicon layers with a doping concentration greater than approximately 1×10 20 cm -3 ; (i) thermally oxidizing the third polysilicon layer to form a capping oxide layer; (j) etching the capping oxide layer, the control gate material layers, and the inter-gate oxide layer to form control gate lines; (k) etching the floating gate lines using the capping oxide and the control gate lines as masks to form floating gates; and (l) implanting source and drain regions using the control gate lines as masks.

Claim 17

An improved process for fabricating a floating gate transistor in a substrate including the steps of (a) providing a gate oxide layer overlying the substrate, (b) providing a floating gate material layer overlying the gate oxide, (c) providing an inter-gate oxide layer overlying the floating gate material layer, (d) providing control gate material layers overlying the inter-gate oxide layer (e) etching the control gate material layer to form a control gate and (f) etching the floating gate material layer to form a floating gate, characterized in that: said step (d) comprises: (1) providing a first undoped polysilicon layer overlying the inter-gate oxide layer, (2) providing a silicide layer overlying the first polysilicon layer, and (3) providing a second undoped polysilicon layer overlying the silicide layer; and the first and second polysilicon layers are doped after said step (d) and before said step (e).

Claim 18

An improved process for fabricating a floating gate transistor in a substrate including the steps of (a) providing a gate oxide layer overlying the substrate, (b) providing a floating gate material layer overlying the gate oxide, (c) providing an inter-gate oxide layer overlying the floating gate material layer, (d) providing control gate material layers overlying the inter-gate oxide layer (e) etching the control gate material layer to form a control gate and (f) etching the floating gate material layer to form a floating gate, characterized in that: said step (d) comprises: (1) providing a first undoped polysilicon layer overlying the inter-gate oxide layer, (2) providing a silicide layer overlying the first polysilicon layer, and (3) providing a second undoped polysilicon layer overlying the silicide layer; and the first and second polysilicon layers are doped after said step (d) and before said step (e).

Claim 19

A process according to claim 13, further characterized in that the first undoped polysilicon layer, the silicide layer and the second polysilicon layer provided in said step (d) are provided in a sealed vacuum chamber without breaking the seal.

Claim 20

A process according to claim 13, further characterized that said step (d) further comprises (4) providing the first and second polysilicon layer with a doping concentration greater than approximately 1×10 20 cm -3 .