High-speed signal multiplexing circuit for multiplexing high-speed signals

Claim 2

A high-speed signal multiplexing circuit for multiplexing a signal at a high speed, comprising: a plurality of latch means for latching 1-bit data; latch control means, provided for each latch means, for causing the latch means to latch 1-bit data supplied thereto, when the 1-bit data supplied to the latch means differs from 1-bit data which has been latched in the latch means; generating means for generating a read signal for successively reading data latched in said latch means in synchronism with a clock signal; and reading means for successively reading data latched in said plurality of latch means in response to the read signal.

Claim 3

A circuit according to claim 1, wherein each of said latch means is constituted by a flip-flop circuit, each having a data input terminal for receiving data, a control signal input terminal for receiving a control signal for latching the data supplied from the latch control means, and an output terminal for outputting latched data.

Claim 4

A circuit according to claim 1, wherein said latch control means is constituted by an exclusive OR circuit.

Claim 5

A circuit according to claim 1, wherein said generating means is constituted by first and second flip-flop circuits for frequency-dividing a clock signal, first and second inverter circuits for inverting signals frequency-divided by said first and second flip-flop circuits, and a plurality of AND circuits for receiving outputs of said first and second inverter circuits and said first and second flip-flop circuits and generating a read signal.

Claim 6

A circuit according to claim 1, wherein said reading means is constituted by an AND circuit having an input terminal which receives the read signal and another input terminal which receives data output from said latch means.

Claim 7

A high-speed signal multiplexing circuit for multiplexing a signal at a high speed, comprising: a plurality of flip-flop circuits for latching data, each having a data input terminal for receiving data, a control signal input terminal for receiving a control signal for latching the data supplied to the data input terminal, and an output terminal for outputting latched data; a plurality of exclusive OR circuits, output terminals of which are respectively connected to the control signal input terminals of said flip-flop circuits, said exclusive OR circuits outputting a control signal for causing each flip-flop circuit to latch the supplied data, when the supplied data differs from the data which has been latched in the flip-flop circuit; a generating circuit for generating a read signal for successively reading data latched in said flip-flop circuits in synchronism with a clock signal; and a reading circuit for successively reading data latched in said flip-flop circuits in response to the read signal.

Claim 8

A high-speed signal multiplexing circuit for multiplexing a signal at a high speed, comprising: a plurality of flip-flop circuits for latching data, each having a data input terminal for receiving data, a control signal input terminal for receiving a control signal for latching the data supplied to the data input terminal, and an output terminal for outputting latched data; a plurality of exclusive OR circuits, output terminals of which are respectively connected to the control signal input terminals of said flip-flop circuits, said exclusive OR circuits outputting a control signal for causing each flip-flop circuit to latch the supplied data, when the supplied data differs from the data which has been latched in the flip-flop circuit; a generating circuit for generating a read signal for successively reading data latched in said flip-flop circuits in synchronism with a clock signal; and a reading circuit for successively reading data latched in said flip-flop circuits in response to the read signal.

Claim 9

A circuit according to claim 6, wherein said generating circuit is constituted by first and second flip-flop circuits for frequency-dividing a clock signal, first and second inverter circuits for inverting signals frequency-divided by said first and second flip-flop circuits, and a plurality of AND circuits for receiving outputs of said first and second inverter circuits and said first and second flip-flop circuits and generating read signals.

Claim 10

A circuit according to claim 6, wherein said reading circuit is constituted by an AND circuit having an input terminal which receives the read signals and having another input terminal which receives data output from said flip-flop circuits.

Claim 11

A circuit for extracting an updated signal, comprising: a flip-flop circuit for latching data, having a data input terminal for receiving data, a control signal input terminal for receiving a control signal for latching the data supplied to the input terminal, and an output terminal for outputting the latched data; and an exclusive OR circuit having an output terminal which is connected to the control signal input terminal of said flip-flop circuit, said exclusive OR circuit outputting a control signal for causing the flip-flop circuit to latch the supplied data, when the supplied data differs from the data which has been latched in the flip-flop circuit.

Claim 12

A circuit for extracting an updated signal, comprising: a flip-flop circuit for latching data, having a data input terminal for receiving data, a control signal input terminal for receiving a control signal for latching the data supplied to the input terminal, and an output terminal for outputting the latched data; and an exclusive OR circuit having an output terminal which is connected to the control signal input terminal of said flip-flop circuit, said exclusive OR circuit outputting a control signal for causing the flip-flop circuit to latch the supplied data, when the supplied data differs from the data which has been latched in the flip-flop circuit.

Claim 13

A circuit according to claim 6, wherein each of said exclusive OR circuits has a pair of input terminals and respective buffer circuits are respectively connected to said input terminal pairs of said exclusive OR circuits.

Claim 14

A circuit according to claim 6, wherein the output terminal of each of said exclusive OR circuits is connected through a buffer circuit to the control signal input terminal of the associated flip-flop circuit.