US4575867A
Expired / Lapsed
US
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High speed programmable prescaler
Assignee: Boeing North American Inc
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Filing: 1982-08-09
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Granted: 1986-03-11
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Expires: 2002-08-09
Abstract
Abstract A high speed programmable prescaler has an input divider that divides an input stream of clock pulses by either 2 or upon command by 3. Connected to the input divider is a plurality of dividers that are electrically cascaded together from a first member to last member with each member of the plurality of dividers being capable of dividing the clock pulses applied to it by either 2 or upon command by 3. A prescaler selects either 2 or 3 for dividing the input stream of clock pulses so that number of clock pulses necessary to obtain an output pulse can be represented by the equation of 2 N +M where N is the number of members of the plurality of dividers and M is the control number having a range of 0 to 2 N -1. The critical path delays are minimized by using a flip-flop in the input divider to divide by 2 and then on command shifting the output of the flip-flop by 180° to obtain the divide by 3 function.
Inventors
- 👤 Noel E. Hogue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:32
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/667
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
239 words
A high speed programmable prescaler comprising: first means forming a first frequency divider circuit for receiving and frequency dividing an input signal by a selectable divisor to provide a first divided output signal; second means coupled to said first means for frequency dividing the first divided output signal, said second means comprising a plurality of frequency divider circuits electrically cascaded and constructed such that each receives an input signal and frequency divides that signal by a selectable divisor to produce a divided output signal, the divided output signal of each divider circuit of said cascaded dividers being coupled as the input signal to the next successive divider circuit of said cascaded dividers, said first divided output signal being coupled as the input signal to the first divider circuit of said cascaded dividers, and the divided output signal of the last divider circuit of said cascaded dividers forming a prescaler output signal; and means responsive to a control signal M and coupled to said first and second means for selecting the divisor of said divider circuits of said first and second means such that the prescaler output signal from said second means has a frequency equal to the frequency of the input signal of said first means divided by 2 N +M, where N is the number of divider circuits in said first and second means, and M is a number having a value from zero to 2 N -1.
Claim 2
Dependent Claim
239 words
A high speed programmable prescaler comprising: first means forming a first frequency divider circuit for receiving and frequency dividing an input signal by a selectable divisor to provide a first divided output signal; second means coupled to said first means for frequency dividing the first divided output signal, said second means comprising a plurality of frequency divider circuits electrically cascaded and constructed such that each receives an input signal and frequency divides that signal by a selectable divisor to produce a divided output signal, the divided output signal of each divider circuit of said cascaded dividers being coupled as the input signal to the next successive divider circuit of said cascaded dividers, said first divided output signal being coupled as the input signal to the first divider circuit of said cascaded dividers, and the divided output signal of the last divider circuit of said cascaded dividers forming a prescaler output signal; and means responsive to a control signal M and coupled to said first and second means for selecting the divisor of said divider circuits of said first and second means such that the prescaler output signal from said second means has a frequency equal to the frequency of the input signal of said first means divided by 2 N +M, where N is the number of divider circuits in said first and second means, and M is a number having a value from zero to 2 N -1.
Claim 3
Dependent Claim
65 words
The high speed programmable prescaler of claim 1 wherein said first means comprises: means for frequency dividing the input signal by a first selected divisor and providing a first selected divided output; and means responsive to said control number M for phase-shifting said first selected divided output by 180° to provide that phase-shifted divided output from said first means as said first divided output signal.
Claim 4
Dependent Claim
23 words
The high speed programmable pescaler of claim 2 wherein said means for frequency dividing and means for phase-shifting are constructed as flip-flop circuits.
Claim 5
Dependent Claim
47 words
The high speed programmable prescaler of claim 2 wherein said means for phase shifting comprises: a strobe flip-flop coupled to be responsive to said control number M for providing a strobe signal to said means for frequency dividing to phaseshift said first selected divided output by 180°.
Claim 6
Dependent Claim
24 words
The high speed programmable prescaler of claim 1 wherein said selectable divisor is a number selected from one of the numbers 2 and 3.
Claim 7
Dependent Claim
65 words
A high speed programmable prescaler comprising: means for receiving an input signal of a selected frequency; and means responsive to a control number M for frequency dividing said input signal a plurality of N times to produce a prescaler output signal which is equal to said input signal divided by 2 N +M, where M is a number having a value of 0-2 N -1.
Claim 8
Dependent Claim
65 words
A high speed programmable prescaler comprising: means for receiving an input signal of a selected frequency; and means responsive to a control number M for frequency dividing said input signal a plurality of N times to produce a prescaler output signal which is equal to said input signal divided by 2 N +M, where M is a number having a value of 0-2 N -1.
Claim 9
Dependent Claim
33 words
The high speed programmable prescaler of claim 6 wherein said means for dividing includes means for selecting a divisor for each of said N divisions from one of the numbers 2 and 3.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-10 | 1989-09-09 | 1990-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-10 | 1993-09-09 | 1994-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-10 | 1997-09-09 | 1998-03-11 | $7700.00 | Window Closed / Lapsed |