Asynchronous circuit with edge-triggered inputs

Claim 2

A circuit that receives asynchronous input signals and generates an active asynchronous output signal, said circuit comprising: a first toggle flip-flop, said first toggle flip-flop having a first enable input, a first clock input, and a first output, said first output of said first toggle flip-flop changing logic states upon occurrence of a predetermined edge of a first asynchronous input signal applied to said first clock input only when enabled by a first enable signal applied to said first enable input; p1 a second toggle flip-flop, said second toggle flip-flop having a second enable input, a second clock input, and a second output, said second output of said second toggle flip-flop changing logic states upon occurrence of a predetermined edge of a second asynchronous input signal only applied to said second clock signal only when enabled by a second enable signal applied to said second enable input; and a logic circuit responsive to said outputs of said flip-flops wherein said logic circuit controls the logic level of said first and second enable signals of said flip-flops such that said first flip-flop is enabled prior to occurrence of said predetermined edge of said first asynchronous input signal and disabled after occurrence of said predetermined edge of said first asynchronous input signal, and wherein said second flip-flop is disabled until occurrence of said predetermined edge of said first asynchronous input signal and enabled after occurrence of said predetermined edge of said first asynchronous input signal, said second flip-flop being subsequently disabled and said first flip-flop being enabled upon occurrence of said predetermined edge of said second asynchronous input signal, wherein said logic circuit further generates said active asynchronous output signal between said predetermined edge of said first asynchronous input signal and said predetermined edge of said second asynchronous input signal.

Claim 3

The circuit defined in claim 1, wherein a reset signal is applied to a reset input of said first and second flip-flops to initialize said circuit, said reset signal further enabling said first flip-flop and disabling said second flip-flop.

Claim 4

The circuit defined in claim 1, further including a third toggle flip-flop having a third enable input, a third clock input, and a third output, said third output of said third toggle flip-flop changing logic states upon occurrence of a predetermined edge of a third asynchronous input signal applied to said third clock input only when enabled by a third enable signal applied to said third enable input, said logic circuit further controlling the logic level of said third enable signal such that said third flip-flop and said second flip-flop are alternately enabled after occurrence of said predetermined edge of said first asynchronous input signal, said third flip flop disabled after occurrence of said predetermined edge of said third asynchronous input signal, wherein said logic circuit is responsive to the outputs of said flip-flops such that said active asynchronous output signal is alternately generated (1) between said predetermined edge of said first asynchronous input signal and said predetermined edge of said second asynchronous input signal and (2) between said predetermined edge of said first asynchronous input signal and said predetermined edge of said third asynchronous input signal.

Claim 5

The circuit defined in claim 3, wherein a reset signal is applied to a reset input of said first, second, and third flip-flops to initialize said circuit, said reset signal further enabling said first flip-flop and disabling said second and third flip-flops

Claim 6

The circuit defined in claim 1, further comprising: a third toggle flip-flop having a third enable input, a third clock input, and a third output, said third output of said third toggle flip-flop changing logic states upon occurrence of a predetermined edge of a third asynchronous input signal applied to said third clock input only when enabled by a third enable signal applied to said third enable input; and a fourth toggle flip-flop having a fourth enable input, a fourth clock input, and a fourth output, said fourth output of said fourth toggle flip-flop changing logic states upon occurrence of a predetermined edge of a fourth asynchronous input signal applied to said fourth clock input only when enabled by a fourth enable signal applied to said fourth enable input, said logic circuit further controlling the logic levels of said first, second, third and fourth enable signals such that said first and third flip-flops are initially enabled prior to the occurrence of said predetermined edge of said first asynchronous input signal and disabled upon occurrence of said predetermined edge of said first asynchronous input signal, said occurrence of said predetermined edge of said first asynchronous input signal further enabling said second flip-flop, said first and third flip-flops enabled upon occurrence of said predetermined edge of said second asynchronous input signal, said occurrence of said predetermined edge of said second asynchronous input signal further disabling said second flip flop, said first and third flip-flops also disabled upon occurrence of said predetermined edge of said third asynchronous input signal, said occurrence of said predetermined edge of said third asynchronous input signal further enabling said fourth flip-flop, said first and third flip-flops also enabled upon occurrence of said predetermined edge of said fourth asynchronous input signal, said occurrence of said predetermined edge of said fourth asynchronous input signal further disabling said fourth flip-flop, wherein said logic circuit further generates said active asynchronous output signal when said second flip-flop or said fourth flip-flop is enabled.

Claim 7

The circuit defined in claim 4, wherein a reset signal is applied to a reset input of said first, second, third, and fourth flip-flops to initialize said circuit, said reset signal further enabling said first and third flip-flops, and disabling said second and fourth flip-flops.

Claim 8

The circuit defined in claim 1, further including a third toggle flip-flop having a third enable input, a third clock input, and a third output, said third output of said third toggle flip-flop changing logic states upon occurrence of a predetermined edge of a third asynchronous input signal applied to said third clock input only when enabled by a third enable signal applied to said third enable input, said logic circuit further responsive to a mode selection signal having first and second states, said logic circuit controlling the logic level of said second and third enable signals such that: said second flip-flop is enabled after occurrence of said predetermined edge of said first asynchronous input signal only when said mode selection signal has said first state so that said output signal is active between said predetermined edge of said first asynchronous input signal and said predetermined edge of said second asynchronous input signal; and said third flip-flop is enabled after occurrence of said predetermined edge of said first asynchronous input signal only when said mode selection signal has said second state so that said output signal is active between said predetermined edge of said first asynchronous input signal and said predetermined edge of said third asynchronous input signal.

Claim 9

The circuit defined in claim 7, wherein a reset signal is applied to a reset input of said first, second, and third flip-flops to initialize said circuit, said reset signal further enabling said first flip-flop and disabling said second and third flip-flops.