High speed state machine

Claim 2

A state machine for generating output signals having states which are a function of the current and previous states of the input signals, with the state machine being controlled by a system clock signal, said state machine comprising: at least one pair of latches, each pair comprising: a first latch means having a first input port means, a first output port means and a first enabling port means coupled to the system clock signal, the signal level on said first input port means being transferred to said first output port means while the signal on said first enabling port means is at a first state, and the signal level on said first output port means being latched while the signal on said first enabling port means is at a second state; and a second latch means having a second input port means, a second output port means, and a second enabling port means coupled to the system clock signal, the signal level on said second input port means being transferred to said second output port means while the signal on said second enabling port means is at the second state, and the signal level on said second output port means being latched while the signal on said second enabling port means is at the first state; and a logic means having a pair of logic input port means and a pair of logic output port means wherein the levels of the signals on said logic output port means are predetermined logic functions of the levels of the signals on said two logic input port means, a first of said logic input port means being coupled to receive the state machine input signals, and the first of said logic output port means forming the state machine output signals; the second of said logic input port means being coupled to said first and second output port means of each of said pair(s) of latches; and the second of said logic output port means being coupled to said first and second input port means of each of said pair(s) of latches.

Claim 3

A state machine according to claim 1 further comprising a multiplexing means having two mux input port means, a mux output port means and a mux select port means receiving the system clock signal for outputting the signals of a first of said two mux input port means when the clock signal is at the first level and outputting the signals of the second of said two mux input port means when the clock signal is at the second level; and wherein said first and second output port means of each of said pair(s) of latches are coupled to said second logic input port means through said multiplexing means, said first mux input port means is coupled to said second latch output port means, said second mux input port means is coupled to said first latch output port means, said mux output port means is coupled to said second logic input port means, and said first logic output port means directly forms the state machine output.

Claim 4

A state machine according to claim 2 wherein said first and second input port means of each latch pair are coupled to receive the same signal from said second logic output port means.

Claim 5

A state machine according to claim 1 wherein said first and second latch output port means are coupled directly to said second logic input port means.

Claim 6

A state machine according to claim 4 wherein said logic means comprises two logic blocks, each logic block having two input port means and two output port means, and said first logic output port means of said logic means comprises said first output port means of said two logic blocks; said first input port means of each logic block being coupled to the state machine input signals; the second input port means of one logic block being coupled to said first output port means of each of said latch pair(s) and said second input port means of said other logic block being coupled to said second output port means of each of said latch pair(s); and said second output port means of said one logic block being coupled to said second input port means of each of said latch pair(s) and said second output port means of said other logic block being coupled to said first input port means of each of said latch pair(s).

Claim 7

A state machine according to claim 5 wherein said two logic blocks are substantially identical.

Claim 8

A state machine according to claim 5 wherein said first output port means of said two logic blocks are coupled to a multiplexing means for selecting the state machine outputs from said logic blocks according to the state of the system clock.

Claim 9

A state machine according to claim 7 wherein said two logic blocks are substantially identical.

Claim 10

In a state machine for generating output signals having states which are a function of the current and previous states of the input signals, with the state machine being controlled by a system clock signal, said state machine comprising a logic means having a pair of logic input port means and a pair of logic output port means wherein the states of the signals on the logic output port means are predetermined logic functions of the states of the signals on the two logic input port means, a first of the logic input port means being coupled to receive the state machine input signals and a first of the logic output port means forming the state machine output signals; at least one high speed state element comprising: a first latch means having a first input port means, a first output port means, and a first enabling port means coupleable to the system clock signal, the signal level on said first input port means being transferred to said first output port means while the signal on said first enabling port means is at a first state, and the signal level on said first output port means being latched while the signal on said first enabling port means is at a second state; and a second latch means having a second input port means, a second output port means, and a second enabling port means coupleable to the system clock signal, the signal level on said second input port means being transferred to said second output port means while the signal on said second enabling port means is at the second state, and the signal level on said second output port means being latched while the signal on said second enabling port means is at the first state; and multiplexing means having two mux input port means, a mux output port means and a mux select port means coupleable to the system clock signal for outputting the signals of a first of said two mux input port means when the clock signal is at a first level and outputting the signals of the second of said two mux input port means when the clock signal is at a second level; said first mux input port means being coupled to said second latch output port means and said second mux input port means being coupled to said first latch output port means; said mux output port means being coupleable to the second one of the logic input port means; and said first and second latch input port means being coupleable to the second of the logic output port means.

Claim 11

In a state machine for generating output signals having states which are a function of the current and previous states of the input signals, with the state machine being controlled by a system clock signal, said state machine comprising a logic means having a pair of logic input port means and a pair of logic output port means wherein the states of the signals on the logic output port means are predetermined logic functions of the states of the signals on the two logic input port means, a first of the logic input port means being coupled to receive the state machine input signals and a first of the logic output port means forming the state machine output signals; at least one high speed state element comprising: a first latch means having a first input port means, a first output port means, and a first enabling port means coupleable to the system clock signal, the signal level on said first input port means being transferred to said first output port means while the signal on said first enabling port means is at a first state, and the signal level on said first output port means being latched while the signal on said first enabling port means is at a second state; and a second latch means having a second input port means, a second output port means, and a second enabling port means coupleable to the system clock signal, the signal level on said second input port means being transferred to said second output port means while the signal on said second enabling port means is at the second state, and the signal level on said second output port means being latched while the signal on said second enabling port means is at the first state; and multiplexing means having two mux input port means, a mux output port means and a mux select port means coupleable to the system clock signal for outputting the signals of a first of said two mux input port means when the clock signal is at a first level and outputting the signals of the second of said two mux input port means when the clock signal is at a second level; said first mux input port means being coupled to said second latch output port means and said second mux input port means being coupled to said first latch output port means; said mux output port means being coupleable to the second one of the logic input port means; and said first and second latch input port means being coupleable to the second of the logic output port means.

Claim 12

In a state machine for generating output signals having states which are a function of the current and previous states of the input signals, with the state machine being controlled by a system clock signal, the state machine comprising logic means having a pair of logic input port means and a pair of logic output port means wherein the levels of the signals on the logic output port means are predetermined logic functions of the levels of the signals on the two logic input port means, a first of the logic input port means being coupled to receive the state machine input signals, the signals on a first of the logic output port means forming the state machine output signals; at least one high speed state element comprising: a first latch means having a first input port means, a first output port means, and a first enabling port means coupleable to the system clock signal, the signal level on said first input port means being transferred to said first output port means while the signal on said first enabling port means is at a first state, and the signal level on said first output port means being latched while the signal on said first enabling port means is at a second state; and a second latch means having a second input port means, a second output port means, and a second enabling port means coupleable to the system clock signal, the signal level on said second input port means being transferred to said second output port means while the signal on said second enabling port means is at the second state, and the signal level on said second output port means being latched while the signal on said second enabling port means is at the first state; said first and second latch input port means being coupleable to the second of the logic output port means; and said first and second latch output port means being coupleable to the second one of the logic input port means.

Claim 13

In a state machine for generating output signals having states which are a function of the current and previous states of the input signals, with the state machine being controlled by a system clock signal, the state machine comprising logic means having a pair of logic input port means and a pair of logic output port means wherein the levels of the signals on the logic output port means are predetermined logic functions of the levels of the signals on the two logic input port means, a first of the logic input port means being coupled to receive the state machine input signals, the signals on a first of the logic output port means forming the state machine output signals; at least one high speed state element comprising: a first latch means having a first input port means, a first output port means, and a first enabling port means coupleable to the system clock signal, the signal level on said first input port means being transferred to said first output port means while the signal on said first enabling port means is at a first state, and the signal level on said first output port means being latched while the signal on said first enabling port means is at a second state; and a second latch means having a second input port means, a second output port means, and a second enabling port means coupleable to the system clock signal, the signal level on said second input port means being transferred to said second output port means while the signal on said second enabling port means is at the second state, and the signal level on said second output port means being latched while the signal on said second enabling port means is at the first state; said first and second latch input port means being coupleable to the second of the logic output port means; and said first and second latch output port means being coupleable to the second one of the logic input port means.

Claim 14

In a state machine according to claim 10 wherein the logic means comprises two logic blocks, each logic block having two input port means and two output port means, the first input port means of each logic block being coupled to the state machine input signals; and the first logic output port means of said logic means comprising the first output port means of the two logic blocks; at least one of said state elements wherein said first output port means of each of said state elements is coupleable to the second input port means of one of the logic blocks; said second output port means of said state elements is coupleable to the second input port means of the other of the logic blocks; said second input port means of each of said state elements is coupleable to the second output port means of the one logic block; and said first input port means of each of said state elements is coupleable to the second output port means of the other logic block.

Claim 17

A method according to claim 12 further comprising inputting the outputs of the pair of latch means into an input port means of a multiplexing means and inputting an output of the multiplexing means into the second input port means of the logic means, wherein the outputs of the latch means are input into the logic means through the multiplexing means, the multiplexing means being controlled by the clock signal.

Claim 18

A method according to claim 12 wherein the state machine input signals are input into one input port means of each of a pair of logic blocks forming the logic means; the outputs of both of the latch means are input into the other inputs of different ones of the pair of logic blocks; and outputs of the pair of logic blocks are input into the input port means of the latch means of the pair of latch means which is different than the latch means which has outputs coupled to the logic blocks.

Claim 19

A method according to claim 14 wherein both logic blocks of the pair of logic blocks are substantially identical.

Claim 20

A method according to claim 14 further comprising inputting outputs of the pair of logic blocks into input port means of multiplexing means, and outputting selected inputs of the multiplexing means as state machine outputs according to the state of the system clock.