EP0225075A2
Expired / Lapsed
EP
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Master slave latch circuit
Assignee: Fujitsu Ltd
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Filing: 1986-11-07
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Granted: —
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Expires: 2006-11-07
Abstract
Abstract A master slave latch circuit is formed by a master latch circuit (11, 12, 13) for outputting a master output signal and a slave latch circuit (12, 14, 15) for outputting a slave output signal (S). A latch gate (12) of the master latch circuit (11, 12, 13) is formed so that it is common with a data gate (12) in the slave latch circuit (12, 14, 15). Accordingly, malfunction of the circuit by racing is avoided and the number of gates is reduced, and thus the advantage of an increase in the density of the circuit is obtained.
Inventors
- 👤 Katuhisa Kubota
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 04:58
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/289; H03K3/027; H03K3/037; H03K3/0372
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
60 words
A master slave latch circuit formed by a master latch circuit (11, 12, 13) for outputting a master output signal and a slave latch circuit (12, 14, 15) for outputting a slave output signal, characterised in that a latch gate (12) of the master latch circuit is formed in common with a data gate (12) of the slave latch circuit.
Claim 2
Dependent Claim
60 words
A master slave latch circuit formed by a master latch circuit (11, 12, 13) for outputting a master output signal and a slave latch circuit (12, 14, 15) for outputting a slave output signal, characterised in that a latch gate (12) of the master latch circuit is formed in common with a data gate (12) of the slave latch circuit.
Claim 3
Dependent Claim
201 words
A master slave latch circuit according to claim 1, comprising: a clock driver gate (CD) for receiving an input clock signal and for outputting a positive phase clock (B) and an inverted phase clock (A), a data gate (11) for receiving one of the output clocks from the clock driver gate (CD) and a data signal (+D); a first latch gate (12) for receiving the other output clock of the clock driver gate; a master output gate (13) for receiving an output of the data gate (11) and an output of the first latch gate (12) and for outputting a master output signal, the master output signal also being input to the first latch gate (12); a second latch gate (15) for receiving the input clock for the clock driver gate (CD) or one of the output clocks from the clock driver gate (CD) as one input; and a slave output gate (14) for receiving an output of the first latch gate (12) as one input, for receiving an output from the second latch gate (15) as another input and for outputting a slave output signal (S), the slave output signal (S) also being input to the second latch gate (15).
References Cited (Backward Citations)
No citation records indexed.
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