Metastable prevent circuit

Claim 2

A metastable prevent circuit comprising, in combination: an input for receiving an asynchronous signal containing asynchronous pulses; a plurality of circuit means each connected to said input and to a source of synchronous clock signal and each operable to synchronize asynchronous pulses to said clock signal; and shift means connected to said input and responsive to said asynchronous signal for operating successive ones of said circuit means.

Claim 3

Apparatus according to claim 1 wherein there are two circuit means, and said shift means comprises a bistable means.

Claim 4

A metastable prevent circuit comprising, in combination, a plurality of circuit means each operable to synchronize asynchronous pulses to asynchronous clock signal, each of said circuit means comprising a pulse edge detector responsive to an asynchronous pulse to produce an asynchronous output, and bistable circuit means responsive to said asynchronous output and to a clock pulse of said clock signal to produce a synchronous pulse; and shift means responsive to an asysnchronous signal containing successive ones of said a synchronous pulses to operate successive ones of the pulse edge detector means of said plurality of circuit means to respond to respective ones of said asynchronous pulses.

Claim 5

A metastable prevent circuit comprising, in combination, a plurality of circuit means each operable to synchronize asynchronous pulses to asynchronous clock signal, each of said circuit means comprising a pulse edge detector responsive to an asynchronous pulse to produce an asynchronous output, and bistable circuit means responsive to said asynchronous output and to a clock pulse of said clock signal to produce a synchronous pulse; and shift means responsive to an asysnchronous signal containing successive ones of said a synchronous pulses to operate successive ones of the pulse edge detector means of said plurality of circuit means to respond to respective ones of said asynchronous pulses.

Claim 6

Apparatus according to claim 3 wherein each of said bistable circuit means comprises first bistable means responsive to a first clock pulse and said asynchronous output to produce a first output and second bistable means responsive to a second clock pulse following said first clock pulse and to said first output to produce a synchronous pulse.

Claim 7

Apparatus according to claim 4 wherein each of said pulse edge detector means comprises third resettable bistable means, and gate means responsive to the output of said first, second and third bistable means to reset said first and third bistable means.

Claim 8

Apparatus according to claim 5 wherein said third bistable means is a gate-enabled flip-flop having its enable input connected to an individual output of said shift means.

Claim 9

Apparatus according to claim 5 wherein said third bistable means is a J-K flip-flop having its J input connected to an individual output of said shift means.

Claim 10

Apparatus according to claim 5 wherein said third bistable means is a D-type flip-flop having its D input connected to an individual output of said shift means.

Claim 11

Apparatus according to claim 8 further including OR gate means having a first input connected to said individual output of said shift means, a second input connected to the true output of said D-type flip-flop, and an output connected to said D-input.

Claim 12

Apparatus according to claim 3 wherein there are two circuit means, and said shift means comprises a bistable means.

Claim 13

A metastable prevent circuit comprising, in combination, a plurality of circuit means each operable to synchronize asynchronous pulses to a synchronous clock signal, each of said circuit means comprising first bistable means responsive to a first clock pulse of said clock signal and an asynchronous pulse to produce a first output and second bistable means responsive to a second clock pulse following first said clock pulse and to said first output to produce a synchronous pulse; and shift means responsive to an asynchronous signal containing successive ones of said asynchronous pulses to operate successive ones of the circuit means to respond to respective ones of said asynchronous pulses.

Claim 14

A metastable prevent circuit comprising, in combination, a plurality of circuit means each operable to synchronize asynchronous pulses to a synchronous clock signal, each of said circuit means comprising first bistable means responsive to a first clock pulse of said clock signal and an asynchronous pulse to produce a first output and second bistable means responsive to a second clock pulse following first said clock pulse and to said first output to produce a synchronous pulse; and shift means responsive to an asynchronous signal containing successive ones of said asynchronous pulses to operate successive ones of the circuit means to respond to respective ones of said asynchronous pulses.

Claim 15

Apparatus according to claim 11 wherein there are two circuit means, and said shift means comprises a bistable means.

Claim 16

A metastable prevent circuit comprising: first shift responsive to successive asynchronous pulses of an asynchronous signal to provide alternate first and second enable signals; and first and second channels for synchronizing asynchronous pulses to clock pulses of a synchronous clock signal, said first and second channels each comprising: first bistable means having a clock input connected to receive said asynchronous signal and a further input connected to receive a respective first or second enable signal, said first bistable means providing a first output signal in response to an asynchronous pulse and the respective enable signal, second bistable means having an input connected to receive said first output signal and a clock input connected to receive said synchronous clock signal, said second bistable means providing a second output signal in response to a first clock pulse of said clock signal and said first output signal, and third bistable means having an input connected to receive said second output signal and a clock input connected to receive said synchronous clock signal, said third bistable means providing a third output signal in response to a second clock pulse following said first clock pulse and to said second output signal, said third output signal comprising output pulses synchronous with said clock signal, each output pulse corresponding to an asynchronous pulse responded to by said first bistable means.

Claim 17

A metastable prevent circuit comprising: first shift responsive to successive asynchronous pulses of an asynchronous signal to provide alternate first and second enable signals; and first and second channels for synchronizing asynchronous pulses to clock pulses of a synchronous clock signal, said first and second channels each comprising: first bistable means having a clock input connected to receive said asynchronous signal and a further input connected to receive a respective first or second enable signal, said first bistable means providing a first output signal in response to an asynchronous pulse and the respective enable signal, second bistable means having an input connected to receive said first output signal and a clock input connected to receive said synchronous clock signal, said second bistable means providing a second output signal in response to a first clock pulse of said clock signal and said first output signal, and third bistable means having an input connected to receive said second output signal and a clock input connected to receive said synchronous clock signal, said third bistable means providing a third output signal in response to a second clock pulse following said first clock pulse and to said second output signal, said third output signal comprising output pulses synchronous with said clock signal, each output pulse corresponding to an asynchronous pulse responded to by said first bistable means.

Claim 18

Apparatus according to claim 13 further including, in each channel, gate means responsive to said first, second and third output signals to reset said first and second bistable means, said third bistable means being reset by a third clock pulse following said second clock pulse.

Claim 19

Apparatus according to claim 13 wherein said shift means comprises a flip-flop having a clock input connected to receive said asynchronous signal, and having a first output connected to the further input of the first bistable means of said first channel and a second output connected to the further input of the first bistable means of said second channel.

Claim 20

Apparatus according to claim 15 further including, in each channel, gate means responsive to said first, second and third output signals to reset said first and second bistable means, said third bistable means being reset by a third clock pulse following said second clock pulse.

Claim 21

Apparatus according to claim 16 wherein each of said first bistable means is a gate-enabled flip-flop and said further input is the enable input of said flip-flop.

Claim 22

Apparatus according to claim 16 wherein each of said first bistable means is a J-K flip-flop and said further input is the J input of said flip-flop.

Claim 23

Apparatus according to claim 16 wherein each of said first bistable means is a D-type flip-flop and said further input is the D input of said flip-flop.

Claim 24

Apparatus according to claim 19 further including, in each channel, an OR gate having a first input connected to the respective output of said shift means, a second input connected to the output of said D-type flip-flop, and an output connected to said D input.

Claim 25

Apparatus according to claim 15 wherein each of said first bistable means is a gate-enabled flip-flop and said further input in the enable input of said flip-flop.

Claim 26

Apparatus according to claim 15 wherein each of said first bistable means is a J-K flip-flop and said further input is the J input of said flip-flop.

Claim 27

Apparatus according to claim 15 wherein each of said first bistable means is a D-type flip-flop and said further input is the D input of said flip-flop.

Claim 28

Apparatus according to claim 23 further including, in each channel, an OR gate having a first input connected to the respective output of said shift means, a second input connected to the output of said D-type flip-flop, and an output connected to said D input.