US4591737A
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Master-slave multivibrator with improved metastable response characteristic
Assignee: Advanced Micro Devices Inc
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Filing: 1982-12-13
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Granted: 1986-05-27
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Expires: 2002-12-13
Abstract
Abstract A master-slave flip-flop device wherein the master segment employs function and load isolated outputs driven in parallel with cross-coupled latch transistors is described. Signal feed forward may also be provided from a similarly isolated output of the master segment to a device output gate which also receives the otherwise final output of the slave segment. The device is found to exhibit a minimized duration of the undesired metastable state of the master segment and to, thereby, enhance propagation speed in which a stable state is established.
Inventors
- 👤 David L. Campbell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:30
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/26; H03K3/28; H03K3/281; H03K3/286
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
266 words
A master stage of a logic device for providing logic outputs, as logic input controlling loads, to logic inputs of a slave stage, said master stage being responsive to a clock signal and to complementary first and second master data signals, said master stage comprising: (a) master latch means for latching a master logic state including first and second master transistors respectively having a control electrode, a common electrode and a controllable logic state electrode, said first and second master transistor control electrodes resistively receiving said first and second master data signals, respectively, said first and second master transistor controllable logic state electrodes being respectively coupled so as to respectively provide said second and first master data signals, and said common electrodes being coupled to commonly receive said clock signal; (b) first buffer means for generating a first logic output corresponding to said master logic state and for providing said first logic output to a respective first logic input of said slave stage such that said first logic input is independent load isolated from other logic inputs of said slave stage receiving logic outputs from said master stage; and (c) second buffer means for generating a second logic output corresponding to said master logic state and for providing said second logic output to a respective second logic input of said slave stage such that said second logic input is independent load isolated from other logic inputs of said slave stage, said first and second buffer means generating said first and second logic outputs as the true and complement logic states, respectively, of said master logic state.
Claim 2
Dependent Claim
266 words
A master stage of a logic device for providing logic outputs, as logic input controlling loads, to logic inputs of a slave stage, said master stage being responsive to a clock signal and to complementary first and second master data signals, said master stage comprising: (a) master latch means for latching a master logic state including first and second master transistors respectively having a control electrode, a common electrode and a controllable logic state electrode, said first and second master transistor control electrodes resistively receiving said first and second master data signals, respectively, said first and second master transistor controllable logic state electrodes being respectively coupled so as to respectively provide said second and first master data signals, and said common electrodes being coupled to commonly receive said clock signal; (b) first buffer means for generating a first logic output corresponding to said master logic state and for providing said first logic output to a respective first logic input of said slave stage such that said first logic input is independent load isolated from other logic inputs of said slave stage receiving logic outputs from said master stage; and (c) second buffer means for generating a second logic output corresponding to said master logic state and for providing said second logic output to a respective second logic input of said slave stage such that said second logic input is independent load isolated from other logic inputs of said slave stage, said first and second buffer means generating said first and second logic outputs as the true and complement logic states, respectively, of said master logic state.
Claim 3
Dependent Claim
58 words
The master stage of claim 1 further comprising third buffer means for generating a third logic output corresponding to said master logic state and for providing said third logic output to a respective third logic input of said slave stage such that said third logic input is independent load isolated from other logic inputs of said slave stage.
Claim 4
Dependent Claim
50 words
The master stage of claim 2 wherein said slave stage includes an output gate, wherein said third logic input is a feed forward logic input of said output gate and wherein said third buffer means provides said third logic output as a feed forward logic input to said slave stage.
Claim 5
Dependent Claim
89 words
The master stage of claim 2 wherein second and third buffer means respectively comprise transistors having a control electrode, a common electrode and a controllable logic state electrode responsive to said control electrode, each said control electrode being resistively coupled to respective master transistor controllable logic state electrodes of said master latch means so as to be responsive to said master logic state, said controllable logic state electrodes of said second and third buffer means being respectively coupled to said second and third logic inputs of said slave stage.
Claim 6
Dependent Claim
84 words
The master stage of claim 1 wherein said first buffer means comprises a transistor having a control electrode, a common electrode and a controllable logic state electrode responsive to said control electrode, said control electrode being resistively coupled to a respective master transistor controllable logic state electrode of said master latch means so as to be responsive to said master logic state and said controllable logic state electrode of said first buffer means being coupled to said first logic input of said slave stage.
Claim 7
Dependent Claim
241 words
In a flip-flop device having a master and a slave stage, said master stage including means for latching data in response to a clock signal and wherein said latching means comprises first and second gate elements having respective first and second gate control means for sensing data and first and second gate output means for outputting data, said first and second gate control means and said first and second gate output means being cross-coupled so as to provide for the latching of data and whereupon the latched data is provided to said slave stage, an improvement in said master stage comprising: (a) first means for generating first data corresponding to said latched data and for providing said first data to said slave stage while providing for the independent load isolation of said first data with respect to said latched data, said first generating means being resistively coupled to said second gate output means of said latching means so as to permit the sensing of said latched data; and (b) second means for generating second data corresponding to the complement of said latched data and for providing said second data to said slave stage while providing for the independent load isolation of said second data with respect to said latched data and said first data, said second generating means being resistively coupled to said first gate output means of said latching means so as to permit the sensing of said latched data.
Claim 8
Dependent Claim
241 words
In a flip-flop device having a master and a slave stage, said master stage including means for latching data in response to a clock signal and wherein said latching means comprises first and second gate elements having respective first and second gate control means for sensing data and first and second gate output means for outputting data, said first and second gate control means and said first and second gate output means being cross-coupled so as to provide for the latching of data and whereupon the latched data is provided to said slave stage, an improvement in said master stage comprising: (a) first means for generating first data corresponding to said latched data and for providing said first data to said slave stage while providing for the independent load isolation of said first data with respect to said latched data, said first generating means being resistively coupled to said second gate output means of said latching means so as to permit the sensing of said latched data; and (b) second means for generating second data corresponding to the complement of said latched data and for providing said second data to said slave stage while providing for the independent load isolation of said second data with respect to said latched data and said first data, said second generating means being resistively coupled to said first gate output means of said latching means so as to permit the sensing of said latched data.
Claim 9
Dependent Claim
77 words
The device of claim 6 wherein said first generating means comprises a third gate element having a third gate control means for sensing data and a third gate output means for outputting data generated by said third gate element, said third gate control means being resistively coupled to said second gate output means of said latching means, so as to be responsive to said latched data, and said third output means being coupled to said slave stage.
Claim 10
Dependent Claim
91 words
The device of claim 7 further comprising third generating means for respectively generating third data corresponding to said latched data and for providing said respective third corresponding data to said slave stage while providing for the respective independent load isolation of said third corresponding data of said third generating means with respect to said latched data and that of said first and second data, said third generating means being resistively coupled to said second gate output means of said latching means so as to permit the sensing of said latched data.
Claim 11
Dependent Claim
83 words
The device of claim 8 wherein said second and third generating means respectively comprise fourth and fifth gate elements having fourth and fifth gate control means for sensing data and fourth and fifth gate output means for outputting data generated by said first and second gate elements, said fourth and fifth gate control means being resistively coupled to said first and second gate output means of said latching means, respectively, and said fourth and fifth output means being coupled to said slave stage.
Claim 12
Dependent Claim
18 words
The device of claim 9 wherein said first, second, third, fourth and fifth gate elements comprise Schottky-type transistors.
Claim 13
Dependent Claim
190 words
A master-slave flip-flop having a master and a slave stage, said master stage being responsive to a clock signal and complementary binary state input data provided thereto, said flip-flop comprising: (a) means for latching said input data in response to said clock signal, said latching means further including means for respectively providing data corresponding to the true and complementary states of said input data; and (b) a master stage output buffer including: (i) first, second and third transistors respectively having first, second and third control electrodes, first, second and third common electrodes for receiving said clock signal in common and first, second and third controllable state electrodes coupled separately to said slave stage; and (ii) first, second and third resistor means for resistively coupling said latching means to said first, second and third control electrodes such that said first and second transistors provide output data corresponding to either said true or complementary input data from said first and second controllable state electrodes while said third transistor provides output data from said third controllable state electrode corresponding to the complement of the output data provided by said first and second transistors.
Claim 14
Dependent Claim
190 words
A master-slave flip-flop having a master and a slave stage, said master stage being responsive to a clock signal and complementary binary state input data provided thereto, said flip-flop comprising: (a) means for latching said input data in response to said clock signal, said latching means further including means for respectively providing data corresponding to the true and complementary states of said input data; and (b) a master stage output buffer including: (i) first, second and third transistors respectively having first, second and third control electrodes, first, second and third common electrodes for receiving said clock signal in common and first, second and third controllable state electrodes coupled separately to said slave stage; and (ii) first, second and third resistor means for resistively coupling said latching means to said first, second and third control electrodes such that said first and second transistors provide output data corresponding to either said true or complementary input data from said first and second controllable state electrodes while said third transistor provides output data from said third controllable state electrode corresponding to the complement of the output data provided by said first and second transistors.
Claim 15
Dependent Claim
58 words
The flip-flop of claim 11 wherein said latching means comprises fourth and fifth transistors respectively having fourth and fifth control electrodes for respectively sensing said complementary binary state input data, fourth and fifth common electrodes for receiving said clock signal in common and fourth and fifth controllable state electrodes for respectively asserting said complementary binary state input data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-26 | 1989-11-25 | 1990-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-26 | 1993-11-25 | 1994-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-26 | 1997-11-25 | 1998-05-27 | $7700.00 | Window Closed / Lapsed |