Integrated electronic multiplex circuit

Claim 2

An integrated electronic multiplex circuit comprising: a plurality of logic gates connected to receive N individual data signals, said gates connected to be enabled by a start signal having first and second states; a plurality of N flip-flop circuits serially connected to form a shift register wherein a first flip-flop circuit represents the lowest order section of said shift register and each of flip-flop circuits 2 through N represents increasingly higher order sections, each flip-flop circuit including a master and slave sections, each of said master sections having an input for receiving one of said data signals from said logic gates, each of said slave sections having an input connected to an input of the master section of its adjacent higher order flip-flop circuit, each of said master and slave sections having a clock input for receiving a clocking signal having first and second states, each of said master sections of each flip-flop circuit assuming a data state of its respective input in response to said start signal, and all but the slave section of the Nth flip-flop circuit assuming a state of a data signal present at the input of the master section of its adjacent higher order flip-flop circuit; and a data output terminal connected to the slave section of said Nth flip-flop circuit for providing an output serial data signal.

Claim 3

An integrated electronic multiplex circuit as claimed in claim 1, wherein the master section of said first flip-flop circuit assumes a first binary state upon reception of a second state of the start signal and the first state of said clocking signal.

Claim 4

An integrated electronic multiplex circuit as claimed in claim 2 or 1 the master sections as well as the slave sections of the N flip-flop circuits receiving said clocking signal.

Claim 5

An integrated electronic multiplex circuit as claimed in claim 1, wherein the start signal assumes the second state after each of said master sections of said N flip-flop circuits has assumed a state corresponding to the data on its input, the start signal being maintained in the second state during a number of subsequent first states of said clocking signal corresponding to an amount 1 less than the total number, N, of flip-flop circuits.

Claim 6

An integrated electronic multiplex circuit as claimed in claim 4, wherein the master sections and the slave sections, with the exception of the slave section of the highest order flip-flop circuit, include a load input for receiving a load signal, the load inputs of the slave section of the m th flip-flop circuit receiving an identical load signal, where m is greater than or equal to 1 but less than N, a first state of the n th load signal, where n is greater than or equal to 1 but less than N, indicating that the start signal is in the first state and that the master section of the n th flip-flop circuit responding to the data on the n th data input, must be switched from the first to the second binary state.

Claim 7

An integrated electronic multiplex circuit as claimed in claim 5, wherein the n th load signal is generated by an n th NOR-gate having a first input which receives the start signal and a second input which receives the data on the n th data input.

Claim 8

An integrated electronic multiplex circuit as claimed in claim 6, wherein at least one flip-flop circuit includes a first, a second, a third and a fourth inverting circuit, each of which includes a first and a second supply input, an input and an output, the first supply inputs of each flip-flop circuit being connected to a first supply terminal, the input of the first inverting circuit being connected to the output of the second inverting circuit and vice versa, the second supply inputs being connected to a second supply terminal, a first and a second series connection of channels of a first and second and a third and fourth insulated gate field-effect transistor (IGFET), respectively, connecting the output of the first and the second inverting circuit, respectively, to the second supply terminals, the gates of the second and the fourth IGFET receiving the clocking signal while the gates of the first and the third IGFET serve as inputs for the flip-flop circuit, the channel of a fifth IGFET being connected in parallel with the channel of the third IGFET, the gate of the fifth IGFET constituting the load input of the master section of said flip-flop circuit, the output of the third inverting circuit being connected to the input of the fourth inverting circuit and, vice versa a first and a second parallel connection of the channels of a sixth and seventh and an eigth and ninth IGFET, respectively, connecting the second supply input of the third and the fourth inverting circuit, respectively, to the second suppy terminal, the gates of the seventh and eighth IGFET receiving the clock signal, the gate of the sixth and the ninth IGFET being connected to the output of the second and the first inverting circuit, respectively, the channel of a tenth IGFET being connected between the output and the second supply input of the fourth inverting circuit, its gate constituting the output of the flip-flop circuit.

Claim 9

An integrated electronic circuit which includes a multiplex circuit as claimed in claim 7, wherein the inputs of said master sections of said flip-flop circuits are connected to data outputs of a memory field of a memory integrated on the same substrate.