Fail-safe monitoring apparatus

Claim 2

Signal monitoring apparatus, which comprises: a. a plurality of parallel redundant logic elements; b. a plurality of enable elements connected to receive signals transmitted by said parallel redundant logic elements; c. means for supplying cyclic pulses; d. multi-stable circuit means, having a toggle input connected to said pulse supplying means, and associated with the enable elements such that presence of a predetermined signal level at all of said enable elements enables the multi-stable circuit means to respond to said pulse supplying means to assume a sequence of stable states, thereby producing a cyclic output signal; e. indicator means for sensing cyclic signals and providing an indication thereof; and f. means for connecting the multi-stable circuit means output to said indicator means.

Claim 3

The apparatus as defined in claim 1 wherein the multi-stable circuit means and the enable elements comprises a J-K flip-flop.

Claim 4

The apparatus as defined in claim 2 wherein the signal provided by said logic elements has a DC component, and the pulse supplying means is a digital clock circuit.

Claim 5

In combination with a control signal circuit of the type wherein three or more parallel redundant circuit elements are present, the improvement which comprises: a. a plurality of cascaded J-K type bistable circuits, connected to receive DC signals from the parallel redundant circuit elements at the J and K terminals of said bistable circuit such that presence of a predetermined voltage level at a majority of said circuit elements results in presence of said voltage level at all J and K inputs of said bistable circuits; b. means for applying a toggling signal to the clock terminal of the first stage of said cascaded J-K type bistable circuits; c. means adapted to receive the output of the terminal stage of said cascaded J-K type bistable circuits, and to sense the appearance of an AC signal at said output, whereby the existence of DC signals at a majority of said parallel redundant circuit elements is monitored.

Claim 6

In combination with a control signal circuit of the type wherein three or more parallel redundant circuit elements are present, the improvement which comprises: a. a plurality of cascaded J-K type bistable circuits, connected to receive DC signals from the parallel redundant circuit elements at the J and K terminals of said bistable circuit such that presence of a predetermined voltage level at a majority of said circuit elements results in presence of said voltage level at all J and K inputs of said bistable circuits; b. means for applying a toggling signal to the clock terminal of the first stage of said cascaded J-K type bistable circuits; c. means adapted to receive the output of the terminal stage of said cascaded J-K type bistable circuits, and to sense the appearance of an AC signal at said output, whereby the existence of DC signals at a majority of said parallel redundant circuit elements is monitored.

Claim 7

The apparatus of claim 4 wherein the parallel redundant circuit elements are connected to the J and K inputs in subsets of two elements each, each subset being distinct from all other subsets, and all possible distinct subsets are connected to J and K inputs.

Claim 8

The apparatus of claim 5, and a rectifier connected to the final stage of the cascaded J-K type bistable circuits.