Dual integration circuit

Claim 1

A method for integrating the output signal of space based infrared detectors, said method comprising the steps of: a) receiving the output signal of an infrared detector at an input port; b) simultaneously communicating the detector output signal to first and second integration circuits; c) integrating the detector output signal over a first time interval with the first integration circuit; d) simultaneously integrating the detector output signal over a second time interval with the second integration circuit, the second time interval being longer that the first time interval; e) latching a first counter at a first counter value when a first reference ramp signal achieves a preset value relative to the integrated value of the detector output in the first integration circuit; f) outputting the latched first counter value as a digital signal representative of the detector output signal in response to saturation of the second integration circuit; g) latching a second counter at a second counter value when a second reference ramp signal achieves a preset value relative to the integrated value of the detector output in the second integration circuit in response to non-saturation of the second integration circuit; h) overwriting the first counter value with the second counter value in further response to non-saturation of the second integration circuit; and i) outputting the latched second counter value as a digital signal representative of the detector output signal in further response to non-saturation of the second integration circuit.

Claim 2

A method for integrating the output signal of space based infrared detectors, said method comprising the steps of: a) receiving the output signal of an infrared detector at an input port; b) simultaneously communicating the detector output signal to first and second integration circuits; c) integrating the detector output signal over a first time interval with the first integration circuit; d) simultaneously integrating the detector output signal over a second time interval with the second integration circuit, the second time interval being longer that the first time interval; e) latching a first counter at a first counter value when a first reference ramp signal achieves a preset value relative to the integrated value of the detector output in the first integration circuit; f) outputting the latched first counter value as a digital signal representative of the detector output signal in response to saturation of the second integration circuit; g) latching a second counter at a second counter value when a second reference ramp signal achieves a preset value relative to the integrated value of the detector output in the second integration circuit in response to non-saturation of the second integration circuit; h) overwriting the first counter value with the second counter value in further response to non-saturation of the second integration circuit; and i) outputting the latched second counter value as a digital signal representative of the detector output signal in further response to non-saturation of the second integration circuit.