Focal plane analog-to-digital converter

Claim 2

A focal plane analog-to-digital converter for providing noise immune data communications between a detector element on the focal plane of an infrared detector array and a remote processor, the detector element providing an output signal, the analog-to-digital converter receiving externally generated signals including a ramp signal, counter signals, and a clock signal, the analog-to-digital converter comprising: (a) a sample and hold circuit for receiving and storing the output of one dedicated detector element; (b) a comparator responsive to said sample and hold circuit for comparing the amplitude of the stored detector signal to the amplitude of the externally generated ramp signal, said comparator further being responsive to the externally generated clock signal, said clock signal enabling said comparator only when the counter signals are stable to prevent an output from said comparator during counter signal changes of state; (c) a plurality of latches, the number of latches corresponding to the desired resolution of the analog-to-digital process, for latching the value of the externally generated counter signals when the amplitude of the ramp signal is at a fixed potential relative to the amplitude of the detector signal stored in the sample and hold circuit; and (d) wherein said sample and hold circuit, said comparator, and said latches are disposed upon the focal plane of an infrared detector array.

Claim 3

The focal plane analog-to-digital converter as recited in claim 1 wherein said comparator comprises: (a) a first transistor, responsive to the externally generated ramp signal; (b) a second transistor in series with said first transistor, responsive to the output of the sample and hold circuit; (c) a capacitor in series with said second transistor, said capacitor accumulating a charge when said first transistor and said second transistor conduct; (d) wherein said first transistor and said second transistor both conduct when the externally generated ramp signal is at a fixed potential relative to the output of said sample and hold circuit; and (e) wherein the charge accumulated upon said capacitor provides a signal indicating that the externally generated ramp signal is at a fixed potential relative to the output of said sample and hold circuit.

Claim 4

The focal plane analog-to-digital converter as recited in claim 2 further comprising a third transistor in series with said first and second transistors responsive to the externally generated clock signal such that said capacitor can only accumulated a charge during the period of time when the externally generated clock signals are stable.

Claim 5

The focal plane analog-to-digital converter as recited in claim 3 further comprising: (a) an invertor responsive to the charge accumulated upon said capacitor; (b) a fourth transistor responsive to the output of said invertor; and (c) wherein said invertor and said fourth transistor cooperate to maintain the output of said comparator at a given state once a charge has accumulated upon said capacitor to insure the stability of the comparator.

Claim 6

The focal plane analog-to-digital converter as recited in claim 4 wherein said latches are double buffered to permit the output of the latches to be read while a subsequent conversion is occurring simultaneously.

Claim 7

The focal plane analog-to-digital converter as recited in claim 5 wherein each of said latches further comprises: (a) a first capacitor for storing a charge representative of the state of one externally generated counter signal; (b) a second capacitor for storing a preset charge; (c) a first transistor responsive to the charge stored upon said first capacitor, said first transistor discharging said second capacitor when said first transistor conducts; and (d) wherein said first capacitor stores the state of one counter signal while the state of said second capacitor is being used to define the output of the latch.

Claim 8

The focal plane analog-to-digital converter as recited in claim 6 wherein the slope of the ramp signal can be varied to change the gain of the analog-to-digital converter.

Claim 9

The focal plane analog-to-digital converter as recited in claim 7 wherein the slope of the ramp can be varied in real time for each individual detector channel to provide gain normalization.

Claim 10

The focal plane analog-to-digital converter as recited in claim 1 wherein said comparator is responsive to the slope of the ramp signal to change the gain of the analog-to-digital converter.

Claim 11

The focal plane analog-to-digital converter as recited in claim 1 wherein said comparator is responsive to the slope of successive ramp signals such that successive analog-to-digital conversion may be performed at different gains.

Claim 14

The method as recited in claim 11 wherein the step of providing an output from a comparator further comprises the steps of: (a) communicating a ramp signal to a first transistor; (b) communicating the detector signal from the sample and hold circuit to a second transistor which is in series with the first transistor; (c) accumulating a charge upon a capacitor when both the first and second transistor conduct once the ramp signal has increased to a level where it is at a fixed potential relative to the level of the sample and hold circuit output; and (d) storing the state of the counter when a charge has accumulated upon the capacitor, the state of the counter being representative of the amplitude of the detector signal.

Claim 15

The method as recited in claim 11 wherein the step of accumulating a change upon a capacitor utilized a variable slope ramp, the slope being variable between successive analog-to-digital conversion operations such that the gain of the analog-to-digital converter may be varied between successive operations.

Claim 16

The method as recited in claim 11 wherein the step of accumulating a charge upon a capacitor utilizes a variable slope ramp to permit the gain of the analog-to-digital circuit to be varied.

Claim 17

A focal plane analog-to-digital converter for providing noise immune data communications between detector elements on the focal plane of an infrared detector array and a remote processor, the detector element providing an output signal, the analog-to-digital converter receiving an externally generated ramp signal, counter signals, and a clock signal, the analog-to-digital converter comprising: (a) a plurality of sample and hold circuits, the number of sample and hold circuits substantially conforming to the number of detector elements, each sample and hold circuit for receiving and storing the output signal of one dedicated detector element; (b) a comparator responsive to each sample and hold circuit for comparing the amplitude of the stored detector signal to the amplitude of the externally generated ramp signal, said comparator further being responsive to the externally generated clock signal, said clock signal enabling said comparator only when the counter signals are stable to prevent an output from said comparator during counter signal changes of state; (c) a plurality of latches, the number of latches corresponding to the desired resolution of the analog-to-digital process, for latching the value of the externally generating counter signals when the amplitude of the ramp signal is at a fixed potential relative to the amplitude of the detector signal stored in the sample and hold circuit; and (d) wherein said sample and hold circuit, said comparator, and said latches are disposed upon the focal plane of an infrared detector array.

Claim 18

A focal plane analog-to-digital converter for providing noise immune data communications between detector elements on the focal plane of an infrared detector array and a remote processor, the detector element providing an output signal, the analog-to-digital converter receiving an externally generated ramp signal, counter signals, and a clock signal, the analog-to-digital converter comprising: (a) a plurality of sample and hold circuits, the number of sample and hold circuits substantially conforming to the number of detector elements, each sample and hold circuit for receiving and storing the output signal of one dedicated detector element; (b) a comparator responsive to each sample and hold circuit for comparing the amplitude of the stored detector signal to the amplitude of the externally generated ramp signal, said comparator further being responsive to the externally generated clock signal, said clock signal enabling said comparator only when the counter signals are stable to prevent an output from said comparator during counter signal changes of state; (c) a plurality of latches, the number of latches corresponding to the desired resolution of the analog-to-digital process, for latching the value of the externally generating counter signals when the amplitude of the ramp signal is at a fixed potential relative to the amplitude of the detector signal stored in the sample and hold circuit; and (d) wherein said sample and hold circuit, said comparator, and said latches are disposed upon the focal plane of an infrared detector array.