US5198376A
Expired / Lapsed
US
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Method of forming high performance lateral PNP transistor with buried base contact
Assignee: International Business Machines Corp
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Filing: 1992-07-07
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Granted: 1993-03-30
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Expires: 2012-07-07
Abstract
Abstract A high performance PNP lateral bipolar transistor is described, incorporating at least two trenches extending from the upper P - surface of a semiconductor substrate almost to a buried N + layer. The floor of one trench is heavily N-doped to establish a connection between the buried N + layer and an N - diffusion in the walls of the trench. When the trenches are backfilled with P + polysilicon a lateral PNP is formed having a buried base contact.
Inventors
- 👤 Sridhar Divakaruni
- 👤 Badih El-Kareh
- 👤 Eric D. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:18
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/061; Y; Y10; Y10S; Y10S148/00; Y10S148/096
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
153 words
A method for forming a PNP lateral transistor in a substrate comprising: (a) doping a portion of a surface of said substrate with an N-type impurity to form an N + layer; (b) epitaxially growing a lightly P-doped layer on top of said substrate; (c) implanting a heavily doped N + reach-through from the surface of said lightly P-doped layer to said N + layer; (d) providing an oxide layer on the surface of said lightly P-doped layer; (e) slotting said P-doped layer to provide at least two trenches; (f) implanting an N-type impurity in the floor of one of said trenches such that the resulting heavily-doped N implant extends to said N + layer; (g) doping the walls of said one trench with an N-type impurity; (h) filling said trenches with heavily P-doped polysilicon; and (i) providing electrical connections to said P-doped polysilicon and said N + layer by metallizing and patterning.
Claim 2
Independent Claim
153 words
A method for forming a PNP lateral transistor in a substrate comprising: (a) doping a portion of a surface of said substrate with an N-type impurity to form an N + layer; (b) epitaxially growing a lightly P-doped layer on top of said substrate; (c) implanting a heavily doped N + reach-through from the surface of said lightly P-doped layer to said N + layer; (d) providing an oxide layer on the surface of said lightly P-doped layer; (e) slotting said P-doped layer to provide at least two trenches; (f) implanting an N-type impurity in the floor of one of said trenches such that the resulting heavily-doped N implant extends to said N + layer; (g) doping the walls of said one trench with an N-type impurity; (h) filling said trenches with heavily P-doped polysilicon; and (i) providing electrical connections to said P-doped polysilicon and said N + layer by metallizing and patterning.
Claim 3
Dependent Claim
21 words
A method according to claim 1 wherein said oxide layer on the surface of said P-layer is provided by local oxidation.
Claim 4
Dependent Claim
22 words
A method according to claim 1 wherein said oxide layer on the surface of said P-layer is provided by deposition and patterning.
Claim 5
Dependent Claim
204 words
A process for forming an array of lateral transistors on a semiconductor device which comprises: (a) forming a first heavily doped impurity-containing zone of a first impurity type extending over a portion of a semiconductor substrate; (b) forming a second impurity-containing zone of a second impurity type on top of said first zone; (c) providing a reach-through to said first heavily doped zone. (d) forming a first insulating layer on top of said second zone; (e) by means of a first mask, etching a series of trenches etched into said second impurity zone but not reaching said first impurity zone; (f) forming a second, thinner layer of silicon oxide on the walls and floor of said trenches; (g) using a second mask to cover alternating trenches, implanting a heavily doped implantation of an impurity of a first impurity type in the bottom of each unmasked trench, said implantation extending to said heavily-doped first impurity-containing zone; (h) removing said second silicon oxide layer from said unmasked trenches; (i) selectively implanting a sidewall region of a first impurity type in each of said unmasked trenches; (j) removing remaining second silicon oxide layer; and (k) back-filling each trench with polysilicon heavily doped with a second impurity type.
Claim 6
Dependent Claim
204 words
A process for forming an array of lateral transistors on a semiconductor device which comprises: (a) forming a first heavily doped impurity-containing zone of a first impurity type extending over a portion of a semiconductor substrate; (b) forming a second impurity-containing zone of a second impurity type on top of said first zone; (c) providing a reach-through to said first heavily doped zone. (d) forming a first insulating layer on top of said second zone; (e) by means of a first mask, etching a series of trenches etched into said second impurity zone but not reaching said first impurity zone; (f) forming a second, thinner layer of silicon oxide on the walls and floor of said trenches; (g) using a second mask to cover alternating trenches, implanting a heavily doped implantation of an impurity of a first impurity type in the bottom of each unmasked trench, said implantation extending to said heavily-doped first impurity-containing zone; (h) removing said second silicon oxide layer from said unmasked trenches; (i) selectively implanting a sidewall region of a first impurity type in each of said unmasked trenches; (j) removing remaining second silicon oxide layer; and (k) back-filling each trench with polysilicon heavily doped with a second impurity type.
Claim 7
Dependent Claim
27 words
A process according to claim 4 wherein said first impurity type is N, said second impurity type is P, and said process forms a PNP lateral transistor.
Claim 8
Dependent Claim
203 words
A process for forming an array of lateral transistors on a semiconductor device which comprises: (a) forming a first heavily doped impurity-containing zone of a first impurity type extending over a portion of a semiconductor substrate; (b) forming a second impurity-containing zone of a second impurity type on top of said first zone; (c) providing a reach-through to said first heavily doped zone. (d) forming a first non-insulating layer on top of said second zone; (e) by means of a first mask, etching a series of trenches into said second impurity zone but not reaching said first impurity zone; (f) forming a second, thinner layer of silicon oxide on the walls and floor of said trenches; (g) using a second mask to cover alternating trenches, implanting a heavily doped implantation of an impurity of a first impurity type in the bottom of each unmasked trench, said implantation extending to said heavily-doped first impurity-containing zone; (h) removing said second silicon oxide layer from said unmasked trenches; (i) selectively diffusing a sidewall region of a first impurity type in each of said unmasked trenches; (j) removing remaining second silicon oxide layer; and (k) back-filling each trench with polysilicon heavily doped with a second impurity type.
Claim 9
Dependent Claim
203 words
A process for forming an array of lateral transistors on a semiconductor device which comprises: (a) forming a first heavily doped impurity-containing zone of a first impurity type extending over a portion of a semiconductor substrate; (b) forming a second impurity-containing zone of a second impurity type on top of said first zone; (c) providing a reach-through to said first heavily doped zone. (d) forming a first non-insulating layer on top of said second zone; (e) by means of a first mask, etching a series of trenches into said second impurity zone but not reaching said first impurity zone; (f) forming a second, thinner layer of silicon oxide on the walls and floor of said trenches; (g) using a second mask to cover alternating trenches, implanting a heavily doped implantation of an impurity of a first impurity type in the bottom of each unmasked trench, said implantation extending to said heavily-doped first impurity-containing zone; (h) removing said second silicon oxide layer from said unmasked trenches; (i) selectively diffusing a sidewall region of a first impurity type in each of said unmasked trenches; (j) removing remaining second silicon oxide layer; and (k) back-filling each trench with polysilicon heavily doped with a second impurity type.
Claim 10
Dependent Claim
27 words
A process according to claim 6 wherein said first impurity type is N, said second impurity type is P, and said process forms a PNP lateral transistor.
References Cited (Backward Citations)
US3703420A
Cited
US4466178A
Cited
US4466180A
Cited
US5047828A
Cited
US4704786A
Cited
US4492008A
Cited
US4733287A
Cited
JPS60167459A
Cited
US4956305A
Cited
JPS63300554A
Cited
US4980302A
Cited
US4965217A
Cited
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