Generator detecting internal and external ready signals for generating a bus cycle end signal for microprocessor debugging operation

Claim 1

In a debugging microprocessor, in a microprocessor development support system, for elongating a bus cycle in response to an external ready signal from an external device which is accessed by a data access request from said debugging microprocessor, said external ready signal indicating that said external device has prepared data to be supplied to said debugging microprocessor, said debugging microprocessor tracing and analyzing the result of execution of instructions by said debugging microprocessor, a generator comprising: a ready detection circuit receiving said external ready signal from said external device, and a clock signal and an enable signal from said debugging microprocessor, said enable signal being rendered active only when said debugging microprocessor is in a ready condition for accepting data, said ready detection circuit detecting the status of said external ready signal at a timing defined by each clock signal appearing when said enable signal is active, so as to generate an internal ready signal if said external ready signal is active, said debugging microprocessor responding to said internal ready signal to receive data and a control circuit responding to said internal ready signal for generating a bus cycle end signal indicating that data has been received by said debugging microprocessor, for a predetermined period of time starting from a next clock state, said bus cycle end signal being outputted to said microprocessor development support system after said microprocessor detects that said external ready signal is active and therefore said data has been fetched, so that said bus cycle end signal is used to indicate that said data has been fetched by said microprocessor just before generation of said bus cycle end signal.