US4600988A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory-programmable control
Assignee: Siemens AG
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Filing: 1983-09-13
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Granted: 1986-07-15
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Expires: 2003-09-13
Abstract
Abstract A multiprocessor system having a memory-programmable control of the type having a processor unit, coupling memories and input and output modules for transferring signals to and from a process which is to be controlled. Each processor unit is provided with a subprogram and a data memory which can be accessed directly, and a bus control unit releases access to the common system bus always for only one of the processor units. The access sequence and the access duration of the individual processor units to the common bus, via which the signals run to and from the controlled process, are fixed in a bus assignment matrix. In this manner, simple synchronization of the processor units is achieved. Moreover, guaranteed reaction times with respect to the process are possible. In addition to the duration, sequence, and frequency of the bus access of each processor unit in a bus cycle, the latest number bus window which must be seized by each processor unit can also be monitored by a bus monitoring device, thus insuring that guaranteed reaction times are possible.
Inventors
- 👤 Gautan Tendulkar
- 👤 Claus Becker
- 👤 Wolfgang Richter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:45
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/3625
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
325 words
A memory-programmable controller for controlling the process cycle of a processing machine operating a process, the controller comprising a multiprocessor system having a master communications processor unit and a plurality of individual processor units, each processor unit including a coupling memory, each coupling memory coupling a respective processor unit to a common system bus, and further comprising input/output means coupled to said common system bus for transferring signals from the common system bus to and from the processing machine, said communications processor unit controlling the transfer of signals between the processor units and said processing machine, each processor unit further comprising subprogram memory means and data memory means which can be accessed directly by said communications processor unit, said communications processor unit comprising means for controlling the access of said processor units to the common system bus, said means for controlling comprising bus control unit means for providing access to the common system bus by only one of the processor units at a time, said bus control unit means comprising memory means having stored therein the access sequence of said processor units and the respective access duration times of the processor units to the common system bus, said access duration times comprising selectable integral multiples of a basic clock period, and further comprising means responsive to said stored access sequence and duration times for scanning a bus cycle, said bus cycle comprising a predetermined number of basic clock periods, and means for generating bus release signals, said bus release signals being coupled to respective ones of said processor units for providing access by said respective processor units to the common system bus during said bus cycle and further comprising means for monitoring the number of times the common system bus has been accessed by each processor unit within a predetermined number of bus release signals, said monitoring means comprising counter means for counting out respective predetermined periods of time for each of said processor units.
Claim 2
Dependent Claim
325 words
A memory-programmable controller for controlling the process cycle of a processing machine operating a process, the controller comprising a multiprocessor system having a master communications processor unit and a plurality of individual processor units, each processor unit including a coupling memory, each coupling memory coupling a respective processor unit to a common system bus, and further comprising input/output means coupled to said common system bus for transferring signals from the common system bus to and from the processing machine, said communications processor unit controlling the transfer of signals between the processor units and said processing machine, each processor unit further comprising subprogram memory means and data memory means which can be accessed directly by said communications processor unit, said communications processor unit comprising means for controlling the access of said processor units to the common system bus, said means for controlling comprising bus control unit means for providing access to the common system bus by only one of the processor units at a time, said bus control unit means comprising memory means having stored therein the access sequence of said processor units and the respective access duration times of the processor units to the common system bus, said access duration times comprising selectable integral multiples of a basic clock period, and further comprising means responsive to said stored access sequence and duration times for scanning a bus cycle, said bus cycle comprising a predetermined number of basic clock periods, and means for generating bus release signals, said bus release signals being coupled to respective ones of said processor units for providing access by said respective processor units to the common system bus during said bus cycle and further comprising means for monitoring the number of times the common system bus has been accessed by each processor unit within a predetermined number of bus release signals, said monitoring means comprising counter means for counting out respective predetermined periods of time for each of said processor units.
Claim 3
Dependent Claim
43 words
The memory-programmable controller recited in claim 1, further comprising clock generator means for generating clock pulses having said basic clock period, said clock generator means comprising a clock generator contained in said bus control unit means or means contained in said processing machine.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-14 | 1990-01-13 | 1990-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-14 | 1994-01-13 | 1994-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-14 | 1998-01-13 | 1998-07-15 | $7700.00 | Window Closed / Lapsed |