US4720811A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor capable of stopping its operation at any cycle time
Assignee: Hitachi Ltd
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Filing: 1986-04-25
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Granted: 1988-01-19
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Expires: 2006-04-25
Abstract
Abstract Herein disclosed is a method of controlling a microprocessor in accordance with the present invention characterized in that, when the microprocessor for executing a microprogram in accordance with clock cycles Φ 1 and Φ 2 receives a command (i.e., STOP signal) for stopping a normal operation from the outside, a freezing signal (i.e., FRZ signal) synchronizing with the clock cycles is generated to bring the operation being executed into a stopped state.
Inventors
- 👤 Noboru Yamaguchi
- 👤 Kunio Uchiyama
- 👤 Haruo Koizumi
- 👤 Yoshimune Hagiwara
- 👤 Tadahiko Nishimukai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:07
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0766
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
350 words
A microprocessor comprising: (1) a logic circuit for effecting a desired logic operation; (2) a timing pulse generator circuit for generating at least a first timing pulse and a second timing pulse; (3) an input flip-flop circuit, an output of which is connected to an input of said logic circuit; (4) an output flip-flop circuit, an input of which is connected to an output of said logic circuit; (5) means coupled to said timing pulse generator circuit for controlling supply an non-supply of said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit, respectively, in response to a first input signal for indicating a test mode and a second input signal for indicating a clock advancing operation; (6) first memory means, an output of which is connected to control said controlling means to supply said first timing pulse to said input flip-flop circuit; (7) second memory means, an output of which is connected to control said controlling means so as to supply said second timing pulse to said output flip-flop circuit; and (8) means for inputting test data into said input flip-flop circuit during said test mode; and wherein said control means includes means for supplying said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit, respectively, during a normal mode of operation; wherein said control means includes means for stopping said supply of said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit in response to said first input signal and for supplying said test data to said input flip-flop circuit from said inputting means during a test mode of operation; and wherein said control means includes means for controlling the supply and non-supply of said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit in response to said second input signal, said output of said first memory means and said output of said second memory means during an advanced mode of operation.
Claim 2
Dependent Claim
350 words
A microprocessor comprising: (1) a logic circuit for effecting a desired logic operation; (2) a timing pulse generator circuit for generating at least a first timing pulse and a second timing pulse; (3) an input flip-flop circuit, an output of which is connected to an input of said logic circuit; (4) an output flip-flop circuit, an input of which is connected to an output of said logic circuit; (5) means coupled to said timing pulse generator circuit for controlling supply an non-supply of said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit, respectively, in response to a first input signal for indicating a test mode and a second input signal for indicating a clock advancing operation; (6) first memory means, an output of which is connected to control said controlling means to supply said first timing pulse to said input flip-flop circuit; (7) second memory means, an output of which is connected to control said controlling means so as to supply said second timing pulse to said output flip-flop circuit; and (8) means for inputting test data into said input flip-flop circuit during said test mode; and wherein said control means includes means for supplying said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit, respectively, during a normal mode of operation; wherein said control means includes means for stopping said supply of said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit in response to said first input signal and for supplying said test data to said input flip-flop circuit from said inputting means during a test mode of operation; and wherein said control means includes means for controlling the supply and non-supply of said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit in response to said second input signal, said output of said first memory means and said output of said second memory means during an advanced mode of operation.
Claim 3
Dependent Claim
23 words
A microprocessor according to claim 1, wherein said first input signal and said second input signal are received from outside of said microprocessor.
References Cited (Backward Citations)
US4387423A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-18 | 1991-07-20 | 1992-01-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-18 | 1995-07-20 | 1996-01-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-18 | 1999-07-20 | 2000-01-19 | $7700.00 | Window Closed / Lapsed |