Patent US5179534A successfully refreshed from Google Patents.
US5179534A
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US
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Method and apparatus for setting desired logic state at internal point of a select storage element
Assignee: CROSS-CHECK TECHNOLOGY Inc A CORP OF DELAWARE
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Filing: 1990-10-23
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Granted: 1993-01-12
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Expires: 2010-10-23
Abstract
Abstract An IC having a test grid structure including intersecting probe lines and control/sense lines is used to apply desired logic states directly to internal transmission paths of select storage elements. A switch is located at each intersection for conducting the desired logic state to the internal transmission path. To achieve overwriting and storage of the desired logic state, the conventional storage element is modified to include a transmission gate activated by an overwrite enable signal. The overwrite enable signal is defined by one or more probe lines. To overwrite the contents of a storage element, the storage element is selected by turning on the switch with a probe line coupled to such switch, while the included transmission gate is disabled by receiving the overwrite enable signal. The logic state of the control/sense line is conducted into the storage element to the included transmission gate where it overwrites the current contents and is stored.
Inventors
- 👤 Kerry M. Pierce
- 👤 Thomas V. Ferry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:36
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356086; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C29/00; G11C29/04
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
94 words
A method for overwriting storage contents of a storage element in an integrated circuit, said storage element having an input for receiving logic signals, by writing a desired logic state to a internal transmission path of the storage element, the method comprising the steps of: enabling said internal transmission path with a test signal; and inputting separately from said input a desired logic state to said storage element directly to said internal transmission path while said internal transmission path is enabled, thereby overwriting the contents of said storage element with said desired logic state.
Claim 2
Independent Claim
94 words
A method for overwriting storage contents of a storage element in an integrated circuit, said storage element having an input for receiving logic signals, by writing a desired logic state to a internal transmission path of the storage element, the method comprising the steps of: enabling said internal transmission path with a test signal; and inputting separately from said input a desired logic state to said storage element directly to said internal transmission path while said internal transmission path is enabled, thereby overwriting the contents of said storage element with said desired logic state.
Claim 3
Dependent Claim
99 words
The method of claim 1, wherein the step of enabling comprises turning on a first switch coupled to said internal transmission path with said test signal, and wherein the step of inputting comprises the steps of selecting said storage element by turning on a second switch coupled to said storage element and conducting through said second switch said desired logic state, said second switch being directly coupled to said internal transmission path of said storage element; and further comprising the step of deselecting said storage element by turning off said second switch after said step of inputting has terminated.
Claim 4
Independent Claim
121 words
A method for overwriting the contents of a first storage element among a plurality of storage elements including said first storage element and a second storage element, said first storage element selectable with a first probe signal, said second storage element selectable with a second probe signal, the method comprising the steps of: selecting said first storage element by activating said first probe signal; enabling an internal transmission path of said first storage element by activating said first and second probe signals; inputting a desired logic state to said internal transmission path while said first storage element is selected and while said internal transmission path is enabled; thereby overwriting the contents of said first storage element with said desired logic state.
Claim 5
Independent Claim
121 words
A method for overwriting the contents of a first storage element among a plurality of storage elements including said first storage element and a second storage element, said first storage element selectable with a first probe signal, said second storage element selectable with a second probe signal, the method comprising the steps of: selecting said first storage element by activating said first probe signal; enabling an internal transmission path of said first storage element by activating said first and second probe signals; inputting a desired logic state to said internal transmission path while said first storage element is selected and while said internal transmission path is enabled; thereby overwriting the contents of said first storage element with said desired logic state.
Claim 6
Independent Claim
156 words
An apparatus for setting a desired logic state at a first storage element of a plurality of storage elements including said first storage element and a second storage element, said first storage element selectable for receiving said desired logic state with a first probe signal, said second storage element selectable with a second probe signal, the apparatus comprising: means for selecting said first storage element to receive said desired logic state, said selecting means being directly coupled to an internal transmission path of said first storage element for passing said desired logic state to said internal transmission path when said selecting means is activated by said first probe signal; means for enabling said internal transmission path of said first storage element in response to an overwrite enable signal; and means for inputting said desired logic state to said internal transmission path while said first storage element is selected and while said internal transmission path is enabled.
Claim 7
Independent Claim
156 words
An apparatus for setting a desired logic state at a first storage element of a plurality of storage elements including said first storage element and a second storage element, said first storage element selectable for receiving said desired logic state with a first probe signal, said second storage element selectable with a second probe signal, the apparatus comprising: means for selecting said first storage element to receive said desired logic state, said selecting means being directly coupled to an internal transmission path of said first storage element for passing said desired logic state to said internal transmission path when said selecting means is activated by said first probe signal; means for enabling said internal transmission path of said first storage element in response to an overwrite enable signal; and means for inputting said desired logic state to said internal transmission path while said first storage element is selected and while said internal transmission path is enabled.
Claim 8
Dependent Claim
21 words
The apparatus of claim 4, further comprising means for generating said overwrite enable signal from said first and second probe signals.
Claim 9
Dependent Claim
14 words
The apparatus of claim 5, in which said generating means comprises a NOR gate.
Claim 10
Dependent Claim
16 words
The apparatus of claim 4, in which said overwrite enable signal comprises said second probe signal.
Claim 11
Dependent Claim
26 words
The apparatus of claim 4, in which said enabling means comprises a pair of CMOS transistors of opposite polarity coupled together at respective sources and drains.
Claim 12
Dependent Claim
43 words
The apparatus of claim 8, in which one of said pair of CMOS transistors receives at a gate terminal a non-inverted overwrite enable signal and the other of said pair of CMOS transistors receives at a gate terminal an inverted overwrite enable signal.
Claim 13
Dependent Claim
46 words
The apparatus of claim 8, in which a gate terminal of one of said pair of CMOS transistors is coupled to said first probe signal and in which a gate of the other of said pair of CMOS transistors is coupled to said second probe signal.
Claim 14
Dependent Claim
24 words
The apparatus of claim 4, in which said enabling means comprises a CMOS transistor having respective on/off states defined by said second probe signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-12 | 1996-07-13 | 1997-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-12 | 2000-07-13 | 2001-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-12 | 2004-07-13 | 2005-01-12 | $7700.00 | Window Closed / Lapsed |