Highly compact EPROM and flash EEPROM devices

Claim 2

A two dimensional array of flash electrically erasable and programmable read only memory cells, comprising: a semiconductor substrate containing in a first direction thereacross alternate source and drain regions that are separated by channel regions, said regions being elongated in a second direction across said substrate that is substantially orthogonal to said first direction, a plurality of control and erase gates elongated in said first direction and alternately provided across the substrate in said second direction, said control and erase gates being insulated from each other and the substrate, a floating gate provided for each cell of the array of cells that extends in said first direction under a control gate and over at least a portion of a channel region to terminate in said second direction outside of said control gate at opposite ends thereof adjacent the erase gates on either side thereof, said floating gate being insulated from said control gate and the substrate, and each of said opposite ends of the floating gate being separated from its adjacent erase gate by a tunnel dielectric contacting opposing faces thereof that are positioned to maintain a capacitive coupling therebetween.

Claim 3

The memory cell array according to claim 1 which additionally includes a plurality of elongated thick layers of field dielectric on said substrate positioned substantially under the individual erase gates, thereby to isolate adjacent memory cells in said second direction.

Claim 4

The memory cell array according to claim 1 wherein the individual erase gates are positioned adjacent said substrate with a thin gate dielectric layer separating each such erase gate from the substrate, thereby to allow field isolation of adjacent memory cells in said second direction by an electric field from the erase gates.

Claim 5

The memory cell array according to claim 1 wherein the floating gates terminate in said second direction with an overlap under a portion of the erase gates, said tunnel dielectric being provided therebetween in the overlap.

Claim 6

The memory cell array according to claim 1 wherein the floating gates terminate in said second direction with sidewalls thereof separated from the erase gates by said tunnel dielectric.

Claim 7

The memory cell array according to claim 1 wherein the floating gates terminate in said second direction with sharp-tipped edges that are separated from the erase gates by the tunnel dielectric.

Claim 8

The memory cell array according to claim 1 wherein the floating gate extends in said first direction over only a first portion of the dimension of said channel portion in said first direction, said control gate extending over substantially the remaining portion of said channel portion and separated therefrom by a thin gate dielectric, thereby forming a split-channel transistor cell array.

Claim 9

The memory cell array according to claim 7 wherein the substrate contains adjacent the drains in the first portion of the channel regions a defined area of a given width being doped with the same type of dopant as the substrate and having a doping concentration sufficiently high that the width of a space charge depletion region formed adjacent said drains under programming voltage bias conditions is not more than said given width.

Claim 10

A two dimensional array of flash electrically erasable and programmable split-channel read only memory cells, comprising: a semiconductor substrate containing in a first direction thereacross alternate source and drain regions that are separated by channel regions, said source and drain regions being elongated in a second direction across said substrate that is substantially orthogonal to said first direction, a two dimensional array of a plurality of similarly dimensioned floating gates spaced apart from one another over channel regions in rows extending in the first direction and columns extending in the second direction, said floating gates extending only a portion of the distance across the channel regions in the first direction and being separated therefrom by gate insulation, said floating gates having a given dimension in said second direction between opposing edges thereof, a plurality of elongated control gates extending in said first direction across rows of floating gates with insulation therebetween and being spaced apart in said second direction, said control gates being positioned entirely over the floating gates in a second direction between their said opposing edges and having a width in the second direction that is less than said given dimension, thereby causing surface regions on the top of the floating gates adjacent at least one of their opposing edges to be positioned out from under the control gates, said control gates additionally being separated from channel regions adjacent the floating gates in a first direction by a layer of gate insulation, a tunnel dielectric layer carried by at least a portion of said floating gate top surface regions, and a plurality of erase gates elongated in said first direction and provided in spaces between at least some of adjacent control gates but insulated therefrom and the substrate, said erase gates extending over the tunnel dielectric layers of said floating gates, said floating gates, said control gates and said erase gates each being formed in different layers of electrically conductive material.

Claim 11

A two dimensional array of flash electrically erasable and programmable split-channel read only memory cells, comprising: a semiconductor substrate containing in a first direction thereacross alternate source and drain regions that are separated by channel regions, said source and drain regions being elongated in a second direction across said substrate that is substantially orthogonal to said first direction, a two dimensional array of a plurality of similarly dimensioned floating gates spaced apart from one another over channel regions in rows extending in the first direction and columns extending in the second direction, said floating gates extending only a portion of the distance across the channel regions in the first direction and being separated therefrom by gate insulation, said floating gates having a given dimension in said second direction between opposing edges thereof, a plurality of elongated control gates extending in said first direction across rows of floating gates with insulation therebetween and being spaced apart in said second direction, said control gates being positioned entirely over the floating gates in a second direction between their said opposing edges and having a width in the second direction that is less than said given dimension, thereby causing surface regions on the top of the floating gates adjacent at least one of their opposing edges to be positioned out from under the control gates, said control gates additionally being separated from channel regions adjacent the floating gates in a first direction by a layer of gate insulation, a tunnel dielectric layer carried by at least a portion of said floating gate top surface regions, and a plurality of erase gates elongated in said first direction and provided in spaces between at least some of adjacent control gates but insulated therefrom and the substrate, said erase gates extending over the tunnel dielectric layers of said floating gates, said floating gates, said control gates and said erase gates each being formed in different layers of electrically conductive material.

Claim 12

A memory cell array according to claim 9 wherein said plurality of erase gates are provided in spaces between each of the control gates, and wherein the insulation between said erase gates and said substrate consist of a thin gate oxide layer in order to provide electric field coupling between the erase gates and the substrate that allows isolation of the memory cells from each other in said second direction.

Claim 13

A memory cell array according to claim 9 wherein said plurality of erase gates are provided in spaces between each of the control gates and periodically spaced in a second direction with a distance between said erase gates that is less than said floating gates given dimension in said second direction, whereby said erase gates overlap said floating gates in an amount determined by the difference between the spacing of the control gates and the given dimension of the floating gates.

Claim 14

A memory cell array according to claim 11 wherein said erase gates are positioned across a surface of said floating gates facing away from said substrate.