Semiconductor device having a universal die size inner lead layout

Claim 1

A semiconductor chip assembly comprising: a substrate including a single non-conductive support layer having a front face and a back face, and a conductive layer having a plurality "n" of conductive leads disposed on one face of the support layer, the conductive layer having a front face and a back face, the back face of the conductive layer in contact with the front face of the support layer, the conductive leads arranged in a generally radial pattern about a central point on the support layer, each of the conductive leads having a width "w" and spaced a distance "d" from one another at their innermost ends, the conductive leads having inward lead ends, the inward lead ends forming a generally square opening of side dimension "s"; a semiconductor die larger than the opening, having a front circuit-containing face and a back face, the back face of the die resting on the front face of the conductive leads and substantially overlapping the inward lead ends, the back face of the die secured with an adhesive to the front face of the non-conductive support layer through the opening in the conductive layer, so that the die is disposed atop and over the opening formed by the inward lead ends of the conductive leads; and bond wires connecting the front face of the die to the front face of the conductive leads, substantially outward of the inward lead ends.