Power-on-reset circuit including integration capacitor

Claim 2

A circuit, comprising: a power-on reset pulse generating circuit, which will generate a pulse at any sudden increase of a power supply voltage; a fully symmetrical pair of cross-coupled logic gates; first and second blocking gates, each of said blocking gates having a first input operatively connected to receive an output of a respective one of said pair of cross-coupled gates and a second input connected to receive pulses generated by said pulse generating circuit, and configured to output a pulse only when both said inputs thereto have respectively predetermined states; a combining gate connected to receive an output of each of said blocking gates and to transmit a pulse which is received from either of said blocking gates; and a feedback connection connected to disable said pair of cross-coupled gates wherever said power supply voltage is active and a power-on reset pulse is not being received by said combing gate.

Claim 3

The circuit of claim 1, wherein said combining gate is a NOR gate.

Claim 4

The circuit of claim 1, wherein said combining gate is an XOR gate.

Claim 5

The circuit of claim 1, wherein each said blocking gate is a NAND gate.

Claim 6

The circuit of claim 1, wherein said pair of cross-coupled gates comprises a pair of NAND gates.

Claim 7

The circuit of claim 1, wherein said pair of cross-coupled gates comprises a pair of NOR gates.

Claim 8

The circuit of claim 1, wherein said pulse generating circuit comprises a weak transistor, gated by the power supply voltage, to ground, and an integration capacitor connecting the drain of said weak transistor to said power supply voltage.

Claim 9

A circuit, comprising: a power-on reset pulse generating circuit, which will generate a pulse at any sudden increase of a power supply voltage; a fully symmetrical pair of cross-coupled logic gates; first and second asymmetric inverters, each of said inverters connected to receive an output of a respective one of said pair of cross-coupled gates; first and second blocking gates, each of said blocking gates operatively connected to an output of a respective one of said asymmetric inverters, and each of said blocking gates connected to receive pulses generated by said pulse generating circuit, and to transmit said pulses only if the respective one of said inverters has a predetermined state; a combining gate connected to receive an output of each of said blocking gates and to transmit a pulse which is received from either of said blocking gates; and a feedback connection connected to disable said propagation of said pulses whenever said power supply voltage is active and a power-on reset pulse is not being received by said combing gate.

Claim 10

A circuit, comprising: a power-on reset pulse generating circuit, which will generate a pulse at any sudden increase of a power supply voltage; a fully symmetrical pair of cross-coupled logic gates; first and second asymmetric inverters, each of said inverters connected to receive an output of a respective one of said pair of cross-coupled gates; first and second blocking gates, each of said blocking gates operatively connected to an output of a respective one of said asymmetric inverters, and each of said blocking gates connected to receive pulses generated by said pulse generating circuit, and to transmit said pulses only if the respective one of said inverters has a predetermined state; a combining gate connected to receive an output of each of said blocking gates and to transmit a pulse which is received from either of said blocking gates; and a feedback connection connected to disable said propagation of said pulses whenever said power supply voltage is active and a power-on reset pulse is not being received by said combing gate.

Claim 11

The circuit of claim 8, wherein said combining gate is a NOR gate.

Claim 12

The circuit of claim 8, wherein said combining gate is an XOR gate.

Claim 13

The circuit of claim 8, wherein each said blocking gate is a NAND gate.

Claim 14

The circuit of claim 8, wherein said pair of cross-coupled gates comprises a pair of NAND gates.

Claim 15

The circuit of claim 8, wherein said pair of cross-coupled gates comprises a pair of NOR gates.

Claim 16

The circuit of claim 8, wherein said pulse generating circuit comprises a weak transistor, gated by the power supply voltage, to ground, and an integration capacitor connecting the drain of said weak transistor to said power supply voltage.

Claim 17

The circuit of claim 8, wherein said asymmetric inverter comprises first and second insulated-gate field effect transistors which are commonly gated, said first transistor thereof being connected to pull an output node toward a first power supply voltage and said second transistor thereof being connected to pull said output node toward a second power supply voltage; wherein, when said first and second transistors both receive a gate voltage which is exactly halfway between said first and second power supply voltages, said first transistor provides a current to said output node which is more than 50% greater than the magnitude of the opposing current provided to said output node by said second transistor.

Claim 18

The circuit of claim 15, wherein said first transistor is an NMOS transistor and said second transistor is a PMOS transistor.

Claim 19

The circuit of claim 15, wherein said first transistor is a PMOS transistor and said second transistor is an NMOS transistor, and said second power supply voltage is ground.

Claim 20

An integrated circuit, comprising: power and ground connections, and signal input and output connections; a power-on reset pulse generating circuit, which will generate a pulse at any sudden increase of a power supply voltage at said power connection; a fully symmetrical pair of cross-coupled logic gates; first and second blocking gates, each of said blocking gates having a first input operatively connected to receive an output of a respective one of said pair of cross-coupled gates and a second input connected to receive pulses generated by said pulse generating circuit, and configured to output a pulse only when both said inputs thereto have respectively predetermined states; a combining gate connected to receive an output of each of said blocking gates and to transmit a pulse which is received from either of said blocking gates; a feedback connection connected to disable said pair of cross-coupled gates whenever said power supply voltage is active and a power-on reset pulse is not being received by said combing gate; and programmable logic circuitry, connected to be powered by said power connection, and incorporating at least some sequential logic operatively connected to said input and output connections, and being connected to receive said power-on reset pulse from said combining gate and to be reset to a known state whenever a power-on reset pulse is received.

Claim 21

An integrated circuit, comprising: power and ground connections, and signal input and output connections; a power-on reset pulse generating circuit, which will generate a pulse at any sudden increase of a power supply voltage at said power connection; a fully symmetrical pair of cross-coupled logic gates; first and second blocking gates, each of said blocking gates having a first input operatively connected to receive an output of a respective one of said pair of cross-coupled gates and a second input connected to receive pulses generated by said pulse generating circuit, and configured to output a pulse only when both said inputs thereto have respectively predetermined states; a combining gate connected to receive an output of each of said blocking gates and to transmit a pulse which is received from either of said blocking gates; a feedback connection connected to disable said pair of cross-coupled gates whenever said power supply voltage is active and a power-on reset pulse is not being received by said combing gate; and programmable logic circuitry, connected to be powered by said power connection, and incorporating at least some sequential logic operatively connected to said input and output connections, and being connected to receive said power-on reset pulse from said combining gate and to be reset to a known state whenever a power-on reset pulse is received.

Claim 22

The integrated circuit of claim 18, wherein said pulse generating circuit comprises a weak transistor, gated by the power supply voltage, to ground, and an integration capacitor connecting the drain of said weak transistor to said power supply voltage.

Claim 23

The integrated circuit of claim 18, further comprising first and second asymmetric inverters, each connected to receive the output of a respective one of said cross-coupled gates; and wherein said first and second blocking gates are each operatively connected to the output of a respective one of said asymmetric inverters; and wherein each said asymmetric inverter comprises first and second insulated-gate field effect transistors which are commonly gated, said first transistor thereof being connected to pull an output node toward a first power supply voltage and said second transistor thereof being connected to pull said output node toward a second power supply voltage; wherein, when said first and second transistors both receive a gate voltage which is exactly halfway between said first and second power supply voltages, said first transistor provides a current to said output node which is more than 50% greater than the magnitude of the opposing current provided to said output node by said second transistor.