Thin film transistor array and method of manufacturing same

Claim 1

A method of manufacturing a thin film transistor array comprising the steps of: forming a semiconductor layer and a protective insulating layer in turn on a gate insulating layer formed on a transparent insulating substrate and a gate electrode on said transparent insulating substrate; forming a positive resist film on said protective insulating layer; patterning said positive resist film by a self-alignment method using said gate electrode as a photomask into a pattern aligned with said gate electrode; patterning said protective insulating layer by using said patterned resist film as a mask into a pattern aligned with said gate electrode; forming an impurity-doped semiconductor layer on said semiconductor layer and said patterned protective insulating layer; forming a metal layer on said impurity-doped semiconductor layer; patterning said metal layer into a specific pattern covering a portion including a channel portion above said gate electrode; patterning said impurity-doped semiconductor layer and said semiconductor layer by using said patterned metal layer as a mask; forming source and drain electrodes on said gate insulating layer and a part of said metal layer not including a portion above said protective insulating layer.

Claim 2

A method of manufacturing a thin film transistor array comprising the steps of: forming a semiconductor layer and a protective insulating layer in turn on a gate insulating layer formed on a transparent insulating substrate and a gate electrode on said transparent insulating substrate; forming a positive resist film on said protective insulating layer; patterning said positive resist film by a self-alignment method using said gate electrode as a photomask into a pattern aligned with said gate electrode; patterning said protective insulating layer by using said patterned resist film as a mask into a pattern aligned with said gate electrode; forming an impurity-doped semiconductor layer on said semiconductor layer and said patterned protective insulating layer; forming a metal layer on said impurity-doped semiconductor layer; patterning said metal layer into a specific pattern covering a portion including a channel portion above said gate electrode; patterning said impurity-doped semiconductor layer and said semiconductor layer by using said patterned metal layer as a mask; forming source and drain electrodes on said gate insulating layer and a part of said metal layer not including a portion above said protective insulating layer.