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US5164803A
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US
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Cmos semiconductor device with an element isolating field shield
Assignee: Mitsubishi Electric Corp
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Filing: 1991-02-19
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Granted: 1992-11-17
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Expires: 2011-02-19
Abstract
Abstract A semiconductor device comprises an MOSFET (13) comprising a switching gate electrode (5) and a field shield MOS structure (11) formed on an element isolating region of a semiconductor substrate (1) and performs the element isolation by applying a bias voltage to the field shield (9). The field shield (9) is provided on the element isolating region of the semiconductor substrate (1) through an insulating film (8). A sidewall spacer (12) having its width set such that the field shield (9) may be an offset gate is formed on the side portion of the field shield (9). Then, source and drain layers (6) are formed on the main surface of the semiconductor substrate (1) so as not to overlap with the field shield (9). According to the semiconductor device, since the field shield (9) is the offset gate, it is possible to set high the threshold value on a parasitic MOS transistor and miniaturize the elements.
Inventors
- 👤 Hiroji Ozaki
- 👤 Shinichi Satoh
- 👤 Takahisa Eimori
- 👤 Wataru Wakamiya
- 👤 Yoshinori Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:24
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; H10W; H10W10/00; H10W10/01; H10W10/051; H10W10/50
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
176 words
A CMOS semiconductor device having two MOSFET's and a plurality of element isolating regions, said CMOS type semiconductor device comprising: a semiconductor substrate having a main surface; a field shield provided on an element isolating region formed over said semiconductor substrate at a region where said MOSFETS are adjacent to each other through a first gate insulating film to perform isolation between circit elements by applying a bias voltage to said field shield to prevent formation of a surface inversion layer; a switching gate electrode in each said MOSFET formed on said semiconductor substrate through a second insulating film in each said MOSFET; and source and drain layers formed at the opposite sides of a channel underlying said switching gate electrode on the main surface of said semiconductor substrate, said source and drain layers being formed spaced apart from said field shield in a direction of said channel so as not to overlap with said field shield, the film thickness of said first gate insulating film being made larger than that of second gate insulating film.
Claim 2
Dependent Claim
176 words
A CMOS semiconductor device having two MOSFET's and a plurality of element isolating regions, said CMOS type semiconductor device comprising: a semiconductor substrate having a main surface; a field shield provided on an element isolating region formed over said semiconductor substrate at a region where said MOSFETS are adjacent to each other through a first gate insulating film to perform isolation between circit elements by applying a bias voltage to said field shield to prevent formation of a surface inversion layer; a switching gate electrode in each said MOSFET formed on said semiconductor substrate through a second insulating film in each said MOSFET; and source and drain layers formed at the opposite sides of a channel underlying said switching gate electrode on the main surface of said semiconductor substrate, said source and drain layers being formed spaced apart from said field shield in a direction of said channel so as not to overlap with said field shield, the film thickness of said first gate insulating film being made larger than that of second gate insulating film.
Claim 3
Dependent Claim
44 words
A semiconductor device in accordance with claim 1, wherein ion implanted layer determining the threshold value of said MOSFET and the threshold value of the parasitic MOS transistor of said field shield MOS structure is formed on the main surface of said semiconductor substrate.
Claim 4
Dependent Claim
28 words
A semiconductor device in accordance with claim 1, wherein the semiconductor device comprises a CMOS device made by combining a p channel MOSFET and an n channel MOSFET.
Claim 5
Dependent Claim
55 words
A semiconductor device in accordance with claim 3, wherein ion implanted layer determining the threshold value of the p channel MOSFET and, the threshold value of the n channel MOSFET and the threshold value of the parasitic MOS transistor of the field shield MOS structure is formed on the main surface of said semiconductor substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-17 | 1996-05-18 | 1996-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-17 | 2000-05-18 | 2000-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-17 | 2004-05-18 | 2004-11-17 | $7700.00 | Window Closed / Lapsed |