Patent US3389882A successfully refreshed from Google Patents.
EP0150993A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A method of fabricating a semiconductor memory structure and a semiconductor memory structure
Assignee: Thorn EMI North America Inc
•
Filing: 1985-01-24
•
Granted: —
•
Expires: 2005-01-24
Abstract
Abstract A method of fabricating a semiconductor memory structure and a semiconductor memory structure having a plurality of memory cells (32, 34, 36), adjacent cells being isolated. The method comprises the steps of developing a relatively thick oxide layer (12) on a silicon substrate (10), etching holes through the oxide layer and implanting impurities in the substrate (10) through said holes to define capacitor regions (16). A dielectric layer (20) is formed over the implants and then a capacitor plate (22) is added over the dielectric layer. The spacing between cells is determined by the etching process, and the method has the advantage that one mask is used for several purposes including defining active transistor areas and the first polysilicon layer. Additional advantages are disclosed including a higher body effect in the isolation transistors, use of a nitride dielectric layer, and a higher, stable threshold voltage in the isolation transistors. Also, modification of the improved process for fabrication of P-channel and N-channel devices can be made.
Inventors
- 👤 Sheffield S. Eaton, Jr.
- 👤 Cheng-Cheng Hu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 12:15
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/30; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
104 words
A method of fabricating a semiconductor memory structure having a plurality of memory cells (32,34,36) each having a respective cell (16,22;35) capacitance, in which isolation between adjacent cells is provided, the method comprising the steps of developing an oxide layer (12) upon a silicon substrate; (10), etching holes (14) through said oxide (12) such that the space between memory cells is determined by an etching process, implanting impurities into the etched holes to form memory cell capacitor regions (16), adjusting the capacitor dielectric by forming a layer of dielectric material (20) over said implants (16), and adding a capacitator plate (22) over said dielectric'layer.
Claim 2
Independent Claim
104 words
A method of fabricating a semiconductor memory structure having a plurality of memory cells (32,34,36) each having a respective cell (16,22;35) capacitance, in which isolation between adjacent cells is provided, the method comprising the steps of developing an oxide layer (12) upon a silicon substrate; (10), etching holes (14) through said oxide (12) such that the space between memory cells is determined by an etching process, implanting impurities into the etched holes to form memory cell capacitor regions (16), adjusting the capacitor dielectric by forming a layer of dielectric material (20) over said implants (16), and adding a capacitator plate (22) over said dielectric'layer.
Claim 3
Dependent Claim
26 words
A method as claimed in Claim 1 wherein said step of implanting impurities into the etched holes to form capacitor regions (16) comprises implanting N-type impurities.
Claim 4
Dependent Claim
31 words
A method as claimed in Claim 1 or 2, wherein said step of adding a capacitor plate (22) comprises depositing a layer of polysilicon over said implanted impurities in said substrate.
Claim 5
Independent Claim
22 words
A method as claimed in any preceding claim wherein said capacitor plate (22) is extended over all of said dielectric layer (20).
Claim 6
Independent Claim
20 words
A method as claimed in any preceding claim, wherein said oxide layer (12) developed on said substrate is relatively thick.
Claim 7
Dependent Claim
20 words
A method as claimed in Claim 5, wherein said relatively thick oxide (12) developed is about one thousand angstroms thick.
Claim 8
Independent Claim
27 words
A method as claimed in any preceding claim, wherein said dielectric (20) is extended over said implanted regions and all unetched portions of said oxide layer (12).
Claim 9
Independent Claim
23 words
A method as claimed in any preceding claim, wherein said dielectric (20) formed over said implants and said oxide layer is silicon nitride.
Claim 10
Dependent Claim
21 words
A method as claimed in claim 8, wherein said silicon nitride layer (20) is about one hundred and fifty angstroms thick.
Claim 11
Independent Claim
22 words
A method as claimed in any preceding claim, further including implanting a threshold voltage adjustment implant (11) into said silicon subtrate (10).
Claim 12
Independent Claim
34 words
A method as claimed in any preceding claim, wherein impurities are implanted into holes etched through the oxide layer (12) to form source and drain regions of transistors (38;48,46;56,58) defined in the semiconductor structure.
Claim 13
Dependent Claim
31 words
A method as claimed in Claim 11, wherein said memory cell capacitor regions (16) form source and drain regions of respective transistors (38) each defined between two adjacent memory cells (34,36).
Claim 14
Dependent Claim
23 words
A method as claimed in Claim 11 or 12, wherein a gate (62) is added over said dielectric layer (20) between cells (32,34,36).
Claim 15
Dependent Claim
12 words
A method as claimed in Claim 13, wherein said gate is grounded.
Claim 16
Independent Claim
89 words
A method of fabricating a semiconductor structure having a plurality of transistors, on transistors being isolated, said method comprising providing an oxide layer (12) upon a silicon substrate (10), etching holes through said oxide layer (12) such that spaces between transistors are defined by an etching process, implanting impurities through said holes (14) into said substrate (10) to form source and drain regions (16) of said transistor, adding a gate terminal (62) for a field-shield transistor over said space between transistors, and tying said gate terminal to ground potential.
Claim 17
Independent Claim
89 words
A method of fabricating a semiconductor structure having a plurality of transistors, on transistors being isolated, said method comprising providing an oxide layer (12) upon a silicon substrate (10), etching holes through said oxide layer (12) such that spaces between transistors are defined by an etching process, implanting impurities through said holes (14) into said substrate (10) to form source and drain regions (16) of said transistor, adding a gate terminal (62) for a field-shield transistor over said space between transistors, and tying said gate terminal to ground potential.
Claim 18
Dependent Claim
14 words
A method as claimed in Claim 15, wherein said added gate terminal is polysilicon.
Claim 19
Dependent Claim
45 words
A method as claimed in Claim 15 or 16, wherein said transistors are N-channel transistors (48,46) having active gates formed by implanting N-type impurities through said holes (14), said gate terminal is tied to ground, and a back bias is provided to said substrate (10).
Claim 20
Dependent Claim
59 words
A method as claimed in claim 15 or 16, wherein said transistors are P-channel transistors (56,58) having active gates, formed by defining an N-well (50) in the substrate (10) and implanting P-type impurities into said substrate through said holes, and wherein said gate terminal is tied to a positive potential, and said substrate is tied to a negative potential.
Claim 21
Dependent Claim
69 words
A semiconductor memory structure having a silicon substrate (10) and a plurality of individual memory cells (32,34,36), the structure comprising an oxide layer (12) over said substrate (10), etched walls (14) in said oxide layer, said walls defining holes and spaces between said holes; impurity implants through said holes and into said substrate, a dielectric layer (20) over said implants, and a capacitor plate (22) over said dielectric region.
Claim 22
Dependent Claim
69 words
A semiconductor memory structure having a silicon substrate (10) and a plurality of individual memory cells (32,34,36), the structure comprising an oxide layer (12) over said substrate (10), etched walls (14) in said oxide layer, said walls defining holes and spaces between said holes; impurity implants through said holes and into said substrate, a dielectric layer (20) over said implants, and a capacitor plate (22) over said dielectric region.
Claim 23
Dependent Claim
20 words
A semiconductor memory structure as claimed in Claim 19, wherein said oxide layer (12) is about one thousand angstroms thick.
Claim 24
Dependent Claim
19 words
A semiconductor memory structure as claimed in Claim 19 or 20, wherein said dielectric layer (20) is silicon nitride.
Claim 25
Dependent Claim
20 words
A semiconductor memory structure as claimed in any of Claims 19 to 21, wherein said capacitor plate (22) is polysilicon.
Claim 26
Dependent Claim
24 words
A semiconductor memory structure as claimed in any of Claims 19 to 22, further comprising threshold voltage adjustment implants (11) in said substrate (10).
Claim 27
Dependent Claim
20 words
A semiconductor memory structure as claimed in any of Claims 19 to 23, wherein said impurity implants are N-type material.
Claim 28
Dependent Claim
71 words
A semiconductor memory structure as claimed in any of Claims 19 to 24, wherein said dielectric layer (20) extends over said walls in said oxide layer and the remaining oxide layer not defined by said hole, and said capacitor plate (22) extends over said dielectric layer (20) whereby a transistor structure (38) is formed between said memory cells by the combination of said substrate, oxide layer, dielectric layer and capacitor plate.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.