US4654828A
Expired / Lapsed
US
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Nonvolatile semiconductor memory
Assignee: Hitachi Ltd
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Filing: 1985-10-15
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Granted: 1987-03-31
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Expires: 2005-10-15
Abstract
Abstract A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal-silicon nitride-silicon dioxide-semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal-silicon dioxide-semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.
Inventors
- 👤 Takaaki Hagiwara
- 👤 Yokichi Itoh
- 👤 Ryuji Kondo
- 👤 Yuji Yatsuda
- 👤 Shinichi Minami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:53
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/69; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
266 words
A nonvolatile semiconductor memory circuit comprising: a memory matrix having a plurality of memory cells formed in a surface region of a semiconductor body of a first conductivity type, each of which memory cells is comprised of a metal-nitride-oxide-semiconductor device having a first channel provided in said surface region of said body and a first region of second conductivity type opposite to said first conductivity type and a metal-insulator-semiconductor device having a second channel provided in the surface region of said semiconductor body and having a second region of second conductivity type opposite to said first conductivity type, wherein said first and second channels are connected in series with one another, wherein the metal-nitride-oxide-semiconductor device has a first insulated gate electrode which is coupled to a writing word line driven by first means for selectively driving said writing word line in a writing mode, and the metal-insulator-semiconductor device has a second insulated gate electrode which is coupled to a reading word line which is separate from said writing word line and which is driven by second means for selectively driving said reading word line in a reading mode and in said writing mode; means for addressing one specific memory cell of said plurality of memory cells by selecting a metal-insulator-semiconductor device of said specific memory cell; and means for applying in an erasing mode an erasing voltage to a substrate of said metal-nitride-oxide-semiconductor device and metal-insulator-semiconductor device while grounding said first and second insulated-gates of the memory cell and for holding said first region of said metal-nitride-oxide-semiconductor device of said memory cell in a floating condition.
Claim 2
Dependent Claim
266 words
A nonvolatile semiconductor memory circuit comprising: a memory matrix having a plurality of memory cells formed in a surface region of a semiconductor body of a first conductivity type, each of which memory cells is comprised of a metal-nitride-oxide-semiconductor device having a first channel provided in said surface region of said body and a first region of second conductivity type opposite to said first conductivity type and a metal-insulator-semiconductor device having a second channel provided in the surface region of said semiconductor body and having a second region of second conductivity type opposite to said first conductivity type, wherein said first and second channels are connected in series with one another, wherein the metal-nitride-oxide-semiconductor device has a first insulated gate electrode which is coupled to a writing word line driven by first means for selectively driving said writing word line in a writing mode, and the metal-insulator-semiconductor device has a second insulated gate electrode which is coupled to a reading word line which is separate from said writing word line and which is driven by second means for selectively driving said reading word line in a reading mode and in said writing mode; means for addressing one specific memory cell of said plurality of memory cells by selecting a metal-insulator-semiconductor device of said specific memory cell; and means for applying in an erasing mode an erasing voltage to a substrate of said metal-nitride-oxide-semiconductor device and metal-insulator-semiconductor device while grounding said first and second insulated-gates of the memory cell and for holding said first region of said metal-nitride-oxide-semiconductor device of said memory cell in a floating condition.
Claim 3
Dependent Claim
51 words
A nonvolatile semiconductor memory according to claim 1, further comprising means for setting in the reading mode the first insulated gate electrode of the memory cell at a certain fixed potential between a threshold voltage of said metal-nitride-oxide-semiconductor device at a written state and a threshold voltage at an erased state.
Claim 4
Dependent Claim
28 words
A nonvolatile semiconductor memory according to claim 2, wherein the first insulated-gate electrode of the memory cell is set substantially at a ground potential in the reading mode.
Claim 5
Dependent Claim
78 words
A nonvolatile semiconductor memory according to claim 1, further comprising means for applying in the writing mode a writing voltage Vp to one selected writing word line, and means for setting up in a writing mode a potential Vc of a channel under a first insulated-gate electrode of one specific memory cell so as to produce a different voltage (Vp-Vc) larger than a voltage necessary for writing on said metal-nitride-oxide-semiconductor device to occur in a predetermined write time.
Claim 6
Dependent Claim
31 words
A nonvolatile semiconductor memory according to claim 1, wherein a said first region of said metal-insulator-semiconductor device is connected to a data line, and the data line is made of aluminum.
Claim 7
Dependent Claim
20 words
A nonvolatile semiconductor memory according to claim 5, wherein said first and second insulated-gate electrodes are made of polycrystalline silicon.
Claim 8
Dependent Claim
37 words
A nonvolatile semiconductor memory according to claim 6, wherein said first and second insulated-gate electrodes are respectively provided integrally with said writing word line and said reading word line each of which is made of polycrystalline silicon.
Claim 9
Dependent Claim
16 words
A nonvolatile semiconductor memory according to claim 1, wherein said metal-insulator-semiconductor transistor is a metal-oxide-semiconductor transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-30 | 1990-09-29 | 1991-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-30 | 1994-09-29 | 1995-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-30 | 1998-09-29 | 1999-03-31 | $7700.00 | Window Closed / Lapsed |