Buffer integrated circuit providing testing interface

Claim 2

A buffer integrated circuit providing a testing interface and comprising: a test enable terminal for receiving a test enable bit therethrough; a test input terminal; a test output terminal; a chip select input terminal; a chip select output terminal; first and second clocked bit latches, in cascade connection between said chip select input terminal and said chip select output terminal, said first and second clocked bit latches for storing a chip select bit and for storing a chip test output enable bit, respectively, as may be received through said chip select input terminal during selective clocking of said first and second clocked bit latches; a first plurality of tristate drivers, N in number, each having a respective data bit input terminal, a respective control bit input terminal and a respective data bit output terminal, which data bit output terminals together form a data output port for said buffer integrated circuit; means for applying data signal bits to the data bit input terminals of said first plurality of tristate drivers; means for applying respective control signal bits to the control bit input terminals of said first plurality of tristate drivers; multiplexer means for selecting to said test output terminal the respective logic condition at any one of the data bit output terminals of said first plurality of tristate drivers; a second plurality of tristate drivers, N in number, included in said multiplexer means, each of said tristate drivers in said second plurality having a respective data bit input terminal connecting to the data bit output terminal of a respective said tristate driver in said first plurality, having a respective control bit input terminal, and having a respective data bit output terminal; a further tristate driver included in said multiplexer means, said further tristate driver having a data bit input terminal to which the data bit output terminals of said tristate drivers in said second plurality thereof each connect, having a control bit input terminal, and having a data bit output terminal connected to said test output terminal; means, responding to said chip test output enable bit being stored in said second clocked bit latch and to a test enable bit being received at said test enable terminal, for applying a respective control bit to the control bit input terminal of said further tristate driver which control bit is of a type that conditions the data bit output terminal of said further tristate driver to provide a relatively low-impedance drive from its data bit output terminal as compared to the condition where a control bit of that type is not applied to the control bit input terminal of said further tristate driver; a first serial-in/parallel-out register being included in said multiplexer means, having a serial input port connected from said test input terminal for receiving test output enable signals one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place connected to each control bit input terminal of said second plurality of tristate drivers; a second serial-in/parallel-out register being included in said means for applying output enable bits to the control bit input terminals of said first plurality of tristate drivers, having a serial input port connected from said test input terminal for receiving output enable signals one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each control bit input terminal of said first plurality of tristate drivers; and respective means corresponding to each tristate driver in said first plurality, responding either to at test enable bit not being received at said test enable terminal or to an output enable bit in the bit place of said second serial-in/parallel-out register corresponding to the control bit input terminal of the corresponding said tristate driver, for applying a control bit to the control bit terminal of that corresponding said tristate driver which control bit is of a type that conditions the data output terminal of that corresponding said tristate driver to provide a relatively low-impedance drive from its data bit output terminal as compared to the condition where a control bit of that type is not applied to the control bit terminal of that corresponding said tristate driver.

Claim 3

A buffer integrated circuit as set forth in claim 1 wherein said first and second clocked bit latches are connected in cascade connection between said chip select input terminal and said chip select output terminal with said first clocked bit latch connected before said second clocked bit latch.

Claim 4

A buffer integrated circuit as set forth in claim 1 wherein said means for applying data signal bits to the data bit input terminals of said first plurality of tristate drivers comprises: a first data input port for said buffer integrated circuit having N parallel bit places therein; respective first switch means for selectively connecting each data bit input terminal of said tristate drivers in said first plurality thereof to a corresponding one of said first data input port bit places, as determined by a respective control bit received by each said first switch means; a third serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving test vectors one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each data bit input terminal of said first plurality of tristate drivers; respective second switch means for selectively connecting each data bit input terminal of said tristate drivers in said first plurality thereof to the corresponding bit place of said third serial-in/parallel-out register, as determined by a respective control bit received by each said second switch means.

Claim 5

A buffer integrated circuit as set forth in claim 3 including: a fourth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said first switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said first switch means; respective first switch control means corresponding to each said first switch means, for applying a respective control bit thereto as causes that said first switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said fourth serial-in/parallel-out register output port being in a first rather than a second logic state; a fifth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said second switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said second switch means; respective second switch control means corresponding to each said second switch means, for applying a respective control bit thereto as causes that second switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said fifth serial-in/parallel-out register being in a first rather than a second logic state; and means responsive to respective commands for supplying clocking signal to said first and second clocked bit latches, to said first serial-in/parallel-out register, to said second serial-in/parallel-out register, to said third serial-in/parallel-out register, to said fourth serial-in/parallel-out register, to said fifth serial-in/parallel-out register, or to none of them.

Claim 6

A buffer integrated circuit as set forth in claim 4 wherein said means responsive to respective commands for supplying clocking signal includes therein: a decoder for determining which of said commands is supplied thereto via a set of instruction lines; means for generating clocking signal; means for applying clocking signal to said first and second clocked bit latches responsive to said decoder receiving said command to supply clocking signal to said first and second clocked bit latches; means for applying clocking signal to said first serial-in/parallel-out register responsive to a test output enable bit being stored in said second clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said first serial-in/parallel-out register; means for applying clocking signal to said second serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said second serial-in/parallel-out register; means for applying clocking signal to said third serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said third serial-in/parallel-out register; means for applying clocking signal to said fourth serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said fourth serial-in/parallel-out register; and means for applying clocking signal to said fifth serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said fifth serial-in/parallel-out register.

Claim 7

A buffer integrated circuit as set forth in claim 3 including: a fourth serial-in/parallel-out register having a serial input port connected from said test input terminal for receiving control bits for each said first switch means and each said second switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each of said first switch means and said second switch means; respective first switch control means corresponding to each said first switch means for applying a respective control bit thereto as causes that said first switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said fourth serial-in/parallel-out register output port being in a first rather than a second logic state; respective second switch control means corresponding to each said second switch means for applying a control bit thereto as causes that said second switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said fourth serial-in/parallel-out register output port is in a first rather than a second logic state; and means responsive to respective commands for supplying clocking signal to said first and second clocked bit latches, to said first serial-in/parallel-out register, to said second serial-in/parallel-out register, to said third serial-in/parallel-out register, to said fourth serial-in/parallel-out register, or to none of them.

Claim 8

A buffer integrated circuit as set forth in claim 6 wherein said means responsive to respective commands for supplying clocking signal includes therein: means for generating clocking signal; a decoder for determining which of said commands is supplied thereto via a set of instruction lines; means for applying clocking signal to said first and second clocked bit latches responsive to said decoder receiving said command to supply clocking signal to said first and second clocked bit latches; means for applying clocking signal to said first serial-in/parallel-out register responsive to a test output enable bit being stored in said second clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said first serial-in/parallel-out register; means for applying clocking signal to said second serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said second serial-in/parallel-out register; means for applying clocking signal to said third serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said third serial-in/parallel-out register; and means for applying clocking signal to said fourth serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said fourth serial-in/parallel-out register.

Claim 9

A buffer integrated circuit as set forth in claim 6 including: means responsive to a further command for supplying clocking signal to said third serial-in/parallel-out register and at the same time conditioning said third serial-in/parallel-out register for circulating the test vectors stored therein.

Claim 10

A buffer integrated circuit as set forth in claim 8 wherein said means responsive to respective commands and said means responsive to a further command together include: a decoder for determining which of said commands is supplied thereto via a set of instruction lines; means for generating clocking signal; means for applying clocking signal to said first and second clocked bit latches responsive to said decoder receiving said command to supply clocking signal to said first and second clocked bit latches; means for applying clocking signal to said first serial-in/parallel-out register responsive to a test output enable bit being stored in said second clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said first serial-in/parallel-out register; means for applying clocking signal to said second serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said second serial-in/parallel-out register; means for applying clocking signal to said third serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said further command or said command to supply clocking signal to said third serial-in/parallel-out register; and means for applying clocking signal to said fourth serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said fourth serial-in/parallel-out register.

Claim 11

A buffer integrated circuit as set forth in claim 3 including: a fourth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said first switch means one bit at a time during selective clocking of that register, and having a parallel output port with a first set of alternate bit places respectively corresponding to each said first switch means and with a second set of alternate bit places respectively corresponding to each said second switch means and interleaving with said first set of alternate bit places; respective first switch control means corresponding to each said first switch means, for supplying a respective control bit thereto as causes that said first switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said fourth serial-in/parallel-out register output port being in a first rather than a second state; respective second switch control means corresponding to each said second switch means, for supplying a respective control bit thereto as causes that said second switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said fourth serial-in/parallel-out register output port is in a first rather than a second state; and means responsive to respective commands for supplying clocking signal to said first and second clocked bit latches, to said first serial-in/parallel-out register, to said second serial-in/parallel-out register, to said third serial-in/parallel-out register, to said fourth serial-in/parallel-out register, or to none of them.

Claim 12

A buffer integrated circuit as set forth in claim 10 wherein said means responsive to respective commands for supplying clocking signal includes therein: means for generating clocking signal; a decoder for determining which of said commands is supplied thereto via a set of instruction lines; means for applying clocking signal to said first and second clocked bit latches responsive to said decoder receiving said command to supply clocking signal to said first and second clocked bit latches; means for applying clocking signal to said first serial-in/parallel-out register responsive to a test output enable bit being stored in said second clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said first serial-in/parallel-out register; means for applying clocking signal to said second serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said second serial-in/parallel-out register; means for applying clocking signal to said third serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said third serial-in/parallel-out register; and means for applying clocking signal to said fourth serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said fourth serial-in/parallel-out register.

Claim 13

A buffer integrated circuit as set forth in claim 10 including: means responsive to a further command for supplying clocking signal to said third serial-in/parallel-out register and at the same time conditioning said third serial-in/parallel-out register for circulating the test vectors stored therein.

Claim 14

A buffer integrated circuit as set forth in claim 12 wherein said means responsive to respective commands and said means responsive to a further command together include: a decoder for determining which of said commands is supplied thereto via a set of instruction lines; means for generating clocking signal; means for applying clocking signal to said first and second clocked bit latches responsive to said decoder receiving said command to supply clocking signal to said first and second clocked bit latches; means for applying clocking signal to said first serial-in/parallel-out register responsive to a test output enable bit being stored in said second clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said first serial-in/parallel-out register; means for applying clocking signal to said second serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said second serial-in/parallel-out register; means for applying clocking signal to said third serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said further command or said command to supply clocking signal to said third serial-in/parallel-out register; and means for applying clocking signal to said fourth serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said fourth serial-in/parallel-out register.

Claim 15

A buffer integrated circuit as set forth in claim 1 wherein said means for applying data signal bits to the control bit input terminals of said first plurality of tristate drivers comprises; first, second and third data input ports for said buffer integrated circuit, each respectively having N parallel bit places therein; a third serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving one bit at a time during selective clocking of that register a triple-modular-redundancy token bit interspersed among other bits, and having a parallel output port with first, second and third bit places therein; means, responsive to said triple-modular-redundancy token bit appearing in the first bit place of the output port of said third serial-in/parallel-out register, for generating a first input enable signal; means, responsive to said triple-modular-redundancy token bit appearing in the second bit place of the output port of said third serial-in/parallel-out register, for generating a second input enable signal; means, responsive to said triple-modular-redundancy token bit appearing in the third bit place of the output port of said third serial-in/parallel-out register, for generating a third input enable signal; a voter circuit of the type performing majority logic on a bit-sliced basis, said voter circuit having first, second and third input ports and having an output port, each of which ports has N respective bit places therein, the N respective bit places of the output port of said voter circuit supplying respective ones of data bits applied to the data bit terminals of said first plurality of tristate drivers; respective first switch means for selectively connecting to each bit place of the first input port of said voter circuit from a respective bit place of said first data input port, as determined by a respective control bit received by each said first switch means; a fourth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving test vectors one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each bit place of the first input port of said voter circuit; respective second switch means for selectively connecting to each bit place of the first input port of said voter circuit from the corresponding bit place of the output port of said fourth serial-in/parallel-out register, as determined by a respective control bit received by each said second switch means; respective third switch means for selectively connecting to each bit place of the second input port of said voter circuit from a respective bit place of said second data input port, as determined by a respective control bit received by each said third switch means; a fifth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving test vectors on bit a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each bit place of the second input port of said voter circuit; respective fourth switch means for selectively connecting to each bit place of the second input port of said voter circuit from the corresponding bit place of the output port of said fifth serial-in/parallel-out register, as determined by a respective control bit received by each said fourth switch means; respective fifth switch means for selectively connecting to each bit place of the third input port of said voter circuit from a respective bit place of said third data input port, as determined by a respective control bit received by each said fifth switch means; a sixth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving test vectors one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each bit place of the third input port of said voter circuit; and respective sixth switch means for selectively connecting to each bit place of the third input port of said voter circuit from the corresponding bit place of the output port of said sixth serial-in/parallel-out register, as determined by a respective control bit received by each said sixth switch means.

Claim 16

A buffer integrated circuit as set forth in claim 14 including: respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively from the second, second and third output ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; and means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response.

Claim 17

A buffer integrated circuit as set forth in claim 15 including: means for ANDing said first bit-error OR response and said first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and said second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and said third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a buffer integrated circuit fault indication.

Claim 18

A buffer integrated circuit as set forth in claim 14 including: a seventh serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said first switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said first switch means; respective first switch control means corresponding to each said first switch means, for supplying a respective control bit thereto as causes that said first switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said seventh serial-in/parallel-out register output port being in a first rather than a second state; an eighth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said second switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said second switch means; respective second switch control means corresponding to each said second switch means, for supplying a respective control bit thereto as causes that said second switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said eighth serial-in/parallel-out register output port is in a first rather than a second state; a ninth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said third switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said third switch means; respective third switch control means corresponding to each said third switch means, for supplying a respective control bit thereto as causes that said third switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said ninth serial-in/parallel-out register output port being in a first rather than a second state; a tenth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said fourth switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said fourth switch means; respective fourth switch control means corresponding to each said fourth switch means, for supplying a respective control bit thereto as causes that said fourth switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said tenth serial-in/parallel-out register output port is in a first rather than a second state; an eleventh serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said fifth switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said fifth switch means; respective fifth switch control means corresponding to each said fifth switch means, for supplying a respective control bit thereto as causes that said fifth switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said eleventh serial-in/parallel-out register output port being in a first rather than a second state; a twelfth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said sixth switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said sixth switch means; respective sixth switch control means corresponding to each said sixth switch means, for supplying a respective control bit thereto as causes that said sixth switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said twelfth serial-in/parallel-out register output port is in a first rather than a second state; and means responsive to respective commands for supplying clocking signal to said first and second clocked bit latches, to said first serial-in/parallel-out register, to said second serial-in/parallel-out register, to said third serial-in/parallel-out register, conditionally to each of said fourth and fifth and sixth serial-in/parallel-out registers, to each of said seventh and ninth and eleventh serial-in/parallel-out registers conditionally, to each of said eighth and tenth and twelfth serial-in/parallel-out registers conditionally, or to none of them.

Claim 19

A buffer integrated circuit as set forth in claim 17 wherein said means responsive to respective commands for supplying clocking signal includes therein: a decoder for determining which of said commands is supplied thereto via a set of instruction lines; means for generating clocking signal; means for applying clocking signal to said first and second clocked bit latches responsive to said decoder receiving said command to supply clocking signal to said first and second clocked bit latches; means for applying clocking signal to said first serial-in/parallel-out register responsive to a test output enable bit being stored in said second clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said first serial-in/parallel-out register; means for applying clocking signal to said second serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said second serial-in/parallel-out register; means for applying clocking signal to said third serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said third serial-in/parallel-out register means for applying clocking signal to said fourth serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated, a chip select bit being stored in said first clocked bit latch, and said decoder receiving said command to supply clocking signal conditionally to each of said fourth, fifth and sixth serial-in/parallel-out registers; means for applying clocking signal to said fifth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated, a chip select bit being stored in said first clocked bit latch, and said decoder receiving a command to said fourth, fifth and sixth serial-in/parallel-out registers; means for applying clocking signal to said sixth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated, a chip select bit being stored in said first clocked bit latch, and said decoder receiving said command to supply clocking signal conditionally to each of said fourth, fifth and sixth serial-in/parallel-out registers; means for applying clocking signal to said seventh serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated, a chip select bit being stored in said first clocked bit latch and said decoder at the same time receiving said command to supply clocking signal conditionally to each of said seventh, ninth and eleventh serial-in/parallel-out registers; means for applying clocking signal to said eighth serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated, a chip select bit being stored in said first clocked bit latch and said decoder at the same time receiving said command to supply clocking signal conditionally to each of said eighth, tenth and twelfth serial-in/parallel-out registers; means for applying clocking signal to said ninth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated, a chip select bit being stored in said first clocked bit latch and said decoder at the same time receiving said command to supply clocking signal conditionally to each of said seventh, ninth and eleventh serial-in/parallel-out registers; means for applying clocking signal to said tenth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated, a chip select bit being stored in said first clocked bit latch, and said decoder receiving said command to supply clocking signal conditionally to each of said eighth, tenth and twelfth serial-in/parallel-out registers; means for applying clocking signal to said eleventh serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated, a chip select bit being stored in said first clocked bit latch, and said decoder receiving said command to supply clocking signal conditionally to each of said seventh, ninth and eleventh serial-in/parallel-out registers; and means for applying clocking signal to said twelfth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated, a chip select bit being stored in said first clocked bit latch, and said decoder receiving said command to supply clocking signal to each of said eighth and tenth and twelfth serial-in/parallel-out registers conditionally.

Claim 20

A buffer integrated circuit as set forth in claim 17 including: respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively at the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; and means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response.

Claim 21

A buffer integrated circuit as set forth in claim 19 including: means for ANDing said first bit-error OR response and said first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and said second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and said third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a buffer integrated circuit fault indication.

Claim 22

A buffer integrated circuit as set forth in claim 14 including: a seventh serial-in/parallel-out register having a serial input port connected from said test input terminal for receiving control bits for each said first switch means and each said second switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each of said first switch means and said second switch means; respective first switch control means corresponding to each said first switch means, for supplying a respective control bit thereto as causes that said first switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said seventh serial-in/parallel-out register output port being in a first rather than a second state; respective second switch control means corresponding to each said second switch means, for supplying a respective control bit thereto as causes that said second switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said seventh serial-in/parallel-out register output port is in a first rather than a second state; an eighth serial-in/parallel-out register having a serial input port connected from said test input terminal for receiving control bits for each said third switch means and each said fourth switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each of said third switch means and said fourth switch means; respective third switch control means corresponding to each said third switch means, for supplying a respective control bit thereto as causes that said third switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said eighth serial-in/parallel-out register output port being in a first rather than a second state; respective fourth switch control means corresponding to each said fourth switch means, for supplying a respective control bit thereto as causes that said fourth switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said eighth serial-in/parallel-out register output port is in a first rather than a second state; a ninth serial-in/parallel-out register having a terminal for receiving control bits for each said fifth switch means and each said sixth switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each of said fifth switch means and said sixth switch means; respective fifth switch control means corresponding to each said fifth switch means, for supplying a respective control bit thereto as causes that said fifth switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said ninth serial-in/parallel-out register output port being in a first rather than a second state; respective sixth switch control means corresponding to each said sixth switch means, for supplying a respective control bit thereto as causes that said sixth switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said ninth serial-in/parallel-out register output port is in a first rather than a second state; and means responsive to respective commands for supplying clocking signal to said first and second clocked bit latches, to said first serial-in/parallel-out register, to said second serial-in/parallel-out register, to said third serial-in/parallel-out register, to each of said fourth and fifth and sixth serial-in/parallel-out registers conditionally, to each of said seventh and eighth and ninth serial-in/parallel-out registers conditionally, or to none of them.

Claim 23

A buffer integrated circuit as set forth in claim 21 wherein said means responsive to respective commands for supplying clocking signal includes therein: a decoder for determining which of said commands is supplied thereto via a set of instruction lines; means for generating clocking signal; means for applying clocking signal to said first and second clocked bit latches responsive to said decoder receiving said command to supply clocking signal to said first and second clocked bit latches; means for applying clocking signal to said first serial-in/parallel-out register responsive to a test output enable bit being stored in said second clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said first serial-in/parallel-out register; means for applying clocking signal to said second serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said second serial-in/parallel-out register; means for applying clocking signal to said third serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said third serial-in/parallel-out register means for applying clocking signal to said fourth serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated, a chip select bit being stored in said first clocked bit latch, and said decoder receiving said command to supply clocking signal conditionally to each of said fourth, fifth and sixth serial-in/parallel-out registers; means for applying clocking signal to said fifth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated, a chip select bit being stored in said first clocked bit latch, and said decoder receiving said command to supply clocking signal conditionally to each of said fourth, fifth and sixth serial-in/parallel-out registers; means for applying clocking signal to said sixth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated, a chip select bit being stored in said first clocked bit latch, and said decoder receiving said command to supply clocking signal conditionally to each of said fourth, fifth and sixth serial-in/parallel-out registers; means for applying clocking signal to said seventh serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated, a chip select bit being stored in said first clocked bit latch and said decoder at the same time receiving said command to supply clocking signal to each of said seventh, eighth and ninth serial-in/parallel-out registers conditionally; means for applying clocking signal to said eighth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated, a chip select bit being stored in said first clocked bit latch and said decoder at the same time receiving said command to supply clocking signal to each of said seventh, eighth and ninth serial-in/parallel-out registers conditionally; and means for applying clocking signal to said ninth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated, a chip select bit being stored in said first clocked bit latch and said decoder at the same time receiving said command to supply clocking signal to each of said seventh, eighth and ninth serial-in/parallel-out registers conditionally.

Claim 24

A buffer integrated circuit as set forth in claim 22 including: respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively at the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; and means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response.

Claim 25

A buffer integrated circuit as set forth in claim 23 including: means for ANDing said first bit-error OR response and said first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and said second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and said third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a buffer integrated circuit fault indication.

Claim 26

A multiplicity of buffer integrated circuits as set forth in claim 24 connecting together groups of integrated circuits of the same type as each other, to form a fault-tolerant electronic system for use with a routing computer that responds to any circuit fault indications from said buffer integrated circuits to attempt to condition said buffer integrated circuits for interconnecting said integrated circuits of other type to provide at least one data path through said fault-tolerant electronic system.

Claim 27

A buffer integrated circuit as set forth in claim 21 including: means responsive to a further command for supplying clocking signal to each of said fourth, fifth and sixth serial-in/parallel-out registers conditionally and at the same time conditioning said fourth, fifth and sixth serial-in/parallel-out registers each for responding to clocking signal supplied thereto to circulate the test vectors stored therein.

Claim 28

A buffer integrated circuit as set forth in claim 26 wherein said means responsive to respective commands and said means responsive to a further command together include: a decoder for determining which of said commands is supplied thereto via a set of instruction lines; means for generating clocking signal; means for applying clocking signal to said first and second clocked bit latches responsive to said decoder receiving said command to supply clocking signal to said first and second clocked bit latches; means for applying clocking signal to said first serial-in/parallel-out register responsive to a test output enable bit being stored in said second clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said first serial-in/parallel-out register; means for applying clocking signal to said second serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said second serial-in/parallel-out register; means for applying clocking signal to said third serial-in/parallel-out register responsive to a chip select bit being stored in said first clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said third serial-in/parallel-out register means for applying clocking signal to said fourth serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated, a chip select bit being stored in said first clocked bit latch, and said decoder receiving either said further command or said command to supply clocking signal to each of said fourth, fifth and sixth serial-in/parallel-out registers conditionally; means for applying clocking signal to said fifth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated, a chip select bit being stored in said first clocked bit latch, and said decoder receiving either said further command said command to supply clocking signal to each of said fourth, fifth and sixth serial-in/parallel-out registers conditionally; means for applying clocking signal to said sixth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated, a chip select bit being stored in said first clocked bit latch, and said decoder receiving either said further command said command to supply clocking signal to each of said fourth, fifth and sixth serial-in/parallel-out registers conditionally; means for applying clocking signal to said seventh serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated, a chip select bit being stored in said first clocked bit latch and said decoder at the same time receiving said command to supply clocking signal to each of said seventh, eighth and ninth serial-in/parallel-out registers conditionally; means for applying clocking signal to said eighth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated, a chip select bit being stored in said first clocked bit latch and said decoder at the same time receiving said command to supply clocking signal to each of said seventh, eighth and ninth serial-in/parallel-out registers conditionally; and means for applying clocking signal to said ninth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated, a chip select bit being stored in said first clocked bit latch and said decoder at the same time receiving said command to supply clocking signal to each of said seventh, eighth and ninth serial-in/parallel-out registers conditionally.

Claim 29

A buffer integrated circuit as set forth in claim 27 including: respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively at the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; and means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response.

Claim 30

A buffer integrated circuit as set forth in claim 28 including: means for ANDing said first bit-error OR response and said first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and said second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and said third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a buffer integrated circuit fault indication.

Claim 31

A multiplicity of buffer integrated circuits as set forth in claim 29 connecting together groups of integrated circuits of the same type as each other, to form a fault-tolerant electronic system for use with a routing computer that responds to any circuit fault indications from said buffer integrated circuits to attempt to condition said buffer integrated circuits for interconnecting said integrated circuits of other type to provide at least one data path through said fault-tolerant electronic system.

Claim 32

A buffer integrated circuit providing a testing interface and comprising: first, second and third data ports for said buffer integrated circuit, each respectively having a number N of parallel bit places therein; a test enable terminal for receiving a test enable bit therethrough; a triple-modular-redundancy enable terminal for receiving a triple-modular-redundancy enable bit therethrough; a test input terminal; a test output terminal; a chip select input terminal; a chip select output terminal; a first plurality of tristate drivers, N in number, each having a respective data bit input terminal, a respective control bit input terminal and a respective data bit output terminal, which data bit output terminals together form a data output port for said buffer integrated circuit; means for applying data signal bits to the data bit input terminals of said first plurality of tristate drivers; means for applying respective control signal bits to the control bit input terminals of said first plurality of tristate drivers; multiplexer means for selecting to said test output terminal the respective logic condition at any one of the data bit output terminals of said first plurality of tristate drivers; a voter circuit of the type performing majority logic on a bit-sliced basis, said voter circuit having first, second and third input ports and having an output port, each of which ports has N respective bit places therein, the N respective bit places of the output port of said voter circuit supplying respective ones of data bits applied to the data bit terminals of said first plurality of tristate drivers; first, second, third and fourth clocked bit latches, in cascade connection between said chip select input terminal and said chip select output terminal, said first, second, third and fourth clocked bit latches for storing a first input data port select bit, for storing a second input data port select bit, for storing a third input data port select bit and for storing a chip test output enable bit, respectively, as may be received through said chip select input terminal during selective clocking of said first and second clocked bit latches; means, responsive to said triple-modular-redundancy enable bit currently being unavailable, for generating a first input enable signal; means, responsive to said first input data port select bit being available, for generating a first input enable signal; means, responsive to said second input data port select bit and said triple-modular-redundancy enable bit being simultaneously available, for generating a second input enable signal; means, responsive to said third input data port select bit and said triple-modular-frequency enable bit being simultaneously available, for generating a third input enable signal; means for ORing said first, second and third input data port select bits to generate a single-bit chip select signal; a second plurality of tristate drivers, N in number, included in said multiplexer means, each of said tristate drivers in said second plurality having a respective data bit input terminal connecting to the data bit output terminal of a respective said tristate driver in said first plurality, having a respective control bit input terminal, and having a respective data bit output terminal; a further tristate driver included in said multiplexer means, said further tristate driver having a data bit input terminal to which the data bit output terminals of said tristate drivers in said second plurality thereof each connect, having a control bit input terminal, and having a data bit output terminal connected to said test output terminal; means, responding to said chip test output enable bit being stored in said fourth clocked bit latch and to a test enable bit being received at said test enable terminal, for applying a respective control bit to the control bit input terminal of said further tristate driver which control bit is of a type that conditions the data bit output terminal of said further tristate driver to provide a relatively low-impedance drive from its data bit output terminal as compared to the condition where a control bit of that type is not applied to the control bit input terminal of said further tristate driver; a first serial-in/parallel-out register being included in said multiplexer means, having a serial input port connected from said test input terminal for receiving test output enable signals one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place connected to each control bit input terminal of said second plurality of tristate drivers; a second serial-in/parallel-out register being included in said means for applying output enable bits to the control bit input terminals of said first plurality of tristate drivers, having a serial input port connected from said test input terminal for receiving output enable signals one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each control bit input terminal of said first plurality of tristate drivers; respective means corresponding to each tristate driver in said first plurality, responding either to a test enable bit not being received at said test enable terminal or to an output enable bit in the bit place of said second serial-in/parallel-out register corresponding to the control bit input terminal of the corresponding said tristate driver, for applying a control bit to the control bit terminal of that corresponding said tristate driver which control bit is of a type that conditions the data output terminal of that corresponding said tristate driver to provide a relatively low-impedance drive from its data bit output terminal as compared to the condition where a control bit of that type is not applied to the control bit terminal of that corresponding said tristate driver; respective first switch means for selectively connecting to each bit pace of the first input port of said voter circuit from a respective bit place of said first data input port, as determined by a respective control bit received by each said first switch means; a third serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving test vectors one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each bit place of the first input port of said voter circuit; respective second switch means for selectively connecting to each bit place of the first input port of said voter circuit from the corresponding bit place of the output port of said third serial-in/parallel-out register, as determined by a respective control bit received by each said second switch means; respective third switch means for selectively connecting to each bit place of the second input port of said voter circuit from a respective bit place of said second data input port, as determined by a respective control bit received by each said third switch means; a fourth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving test vectors one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each bit place of the second input port of said voter circuit; respective fourth switch means for selectively connecting to each bit place of the second input port of said voter circuit from the corresponding bit place of the output port of said fourth serial-in/parallel-out register, as determined by a respective control bit received by each said fourth switch means; respective fifth switch means for selectively connecting to each bit place of the third input port of said voter circuit from a respective bit place of said third data input port, as determined by a respective control bit received by each said fifth switch means; a fifth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving test vectors one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each bit place of the third input port of said voter circuit; and respective sixth switch means for selectively connecting to each bit place of the third input port of said voter circuit from the corresponding bit place of the output port of said fifth serial-in/parallel-out register, as determined by a respective control bit received by each said sixth switch means.

Claim 33

A buffer integrated circuit providing a testing interface and comprising: first, second and third data ports for said buffer integrated circuit, each respectively having a number N of parallel bit places therein; a test enable terminal for receiving a test enable bit therethrough; a triple-modular-redundancy enable terminal for receiving a triple-modular-redundancy enable bit therethrough; a test input terminal; a test output terminal; a chip select input terminal; a chip select output terminal; a first plurality of tristate drivers, N in number, each having a respective data bit input terminal, a respective control bit input terminal and a respective data bit output terminal, which data bit output terminals together form a data output port for said buffer integrated circuit; means for applying data signal bits to the data bit input terminals of said first plurality of tristate drivers; means for applying respective control signal bits to the control bit input terminals of said first plurality of tristate drivers; multiplexer means for selecting to said test output terminal the respective logic condition at any one of the data bit output terminals of said first plurality of tristate drivers; a voter circuit of the type performing majority logic on a bit-sliced basis, said voter circuit having first, second and third input ports and having an output port, each of which ports has N respective bit places therein, the N respective bit places of the output port of said voter circuit supplying respective ones of data bits applied to the data bit terminals of said first plurality of tristate drivers; first, second, third and fourth clocked bit latches, in cascade connection between said chip select input terminal and said chip select output terminal, said first, second, third and fourth clocked bit latches for storing a first input data port select bit, for storing a second input data port select bit, for storing a third input data port select bit and for storing a chip test output enable bit, respectively, as may be received through said chip select input terminal during selective clocking of said first and second clocked bit latches; means, responsive to said triple-modular-redundancy enable bit currently being unavailable, for generating a first input enable signal; means, responsive to said first input data port select bit being available, for generating a first input enable signal; means, responsive to said second input data port select bit and said triple-modular-redundancy enable bit being simultaneously available, for generating a second input enable signal; means, responsive to said third input data port select bit and said triple-modular-frequency enable bit being simultaneously available, for generating a third input enable signal; means for ORing said first, second and third input data port select bits to generate a single-bit chip select signal; a second plurality of tristate drivers, N in number, included in said multiplexer means, each of said tristate drivers in said second plurality having a respective data bit input terminal connecting to the data bit output terminal of a respective said tristate driver in said first plurality, having a respective control bit input terminal, and having a respective data bit output terminal; a further tristate driver included in said multiplexer means, said further tristate driver having a data bit input terminal to which the data bit output terminals of said tristate drivers in said second plurality thereof each connect, having a control bit input terminal, and having a data bit output terminal connected to said test output terminal; means, responding to said chip test output enable bit being stored in said fourth clocked bit latch and to a test enable bit being received at said test enable terminal, for applying a respective control bit to the control bit input terminal of said further tristate driver which control bit is of a type that conditions the data bit output terminal of said further tristate driver to provide a relatively low-impedance drive from its data bit output terminal as compared to the condition where a control bit of that type is not applied to the control bit input terminal of said further tristate driver; a first serial-in/parallel-out register being included in said multiplexer means, having a serial input port connected from said test input terminal for receiving test output enable signals one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place connected to each control bit input terminal of said second plurality of tristate drivers; a second serial-in/parallel-out register being included in said means for applying output enable bits to the control bit input terminals of said first plurality of tristate drivers, having a serial input port connected from said test input terminal for receiving output enable signals one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each control bit input terminal of said first plurality of tristate drivers; respective means corresponding to each tristate driver in said first plurality, responding either to a test enable bit not being received at said test enable terminal or to an output enable bit in the bit place of said second serial-in/parallel-out register corresponding to the control bit input terminal of the corresponding said tristate driver, for applying a control bit to the control bit terminal of that corresponding said tristate driver which control bit is of a type that conditions the data output terminal of that corresponding said tristate driver to provide a relatively low-impedance drive from its data bit output terminal as compared to the condition where a control bit of that type is not applied to the control bit terminal of that corresponding said tristate driver; respective first switch means for selectively connecting to each bit pace of the first input port of said voter circuit from a respective bit place of said first data input port, as determined by a respective control bit received by each said first switch means; a third serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving test vectors one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each bit place of the first input port of said voter circuit; respective second switch means for selectively connecting to each bit place of the first input port of said voter circuit from the corresponding bit place of the output port of said third serial-in/parallel-out register, as determined by a respective control bit received by each said second switch means; respective third switch means for selectively connecting to each bit place of the second input port of said voter circuit from a respective bit place of said second data input port, as determined by a respective control bit received by each said third switch means; a fourth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving test vectors one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each bit place of the second input port of said voter circuit; respective fourth switch means for selectively connecting to each bit place of the second input port of said voter circuit from the corresponding bit place of the output port of said fourth serial-in/parallel-out register, as determined by a respective control bit received by each said fourth switch means; respective fifth switch means for selectively connecting to each bit place of the third input port of said voter circuit from a respective bit place of said third data input port, as determined by a respective control bit received by each said fifth switch means; a fifth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving test vectors one bit at a time during selective clocking of that register and having a parallel output port with a respective bit place corresponding to each bit place of the third input port of said voter circuit; and respective sixth switch means for selectively connecting to each bit place of the third input port of said voter circuit from the corresponding bit place of the output port of said fifth serial-in/parallel-out register, as determined by a respective control bit received by each said sixth switch means.

Claim 34

A buffer integrated circuit as set forth in claim 31 wherein said first, second, third and fourth clocked bit latches are connected in order of their ordinal numbering in their said cascade connection between said chip select input terminal and said chip select output terminal.

Claim 35

A buffer integrated circuit as set forth in claim 31 including: respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively at the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; and means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response.

Claim 36

A buffer integrated circuit as set forth in claim 33 including: means for ANDing said first bit-error OR response and said first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and said second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and said third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a buffer integrated circuit fault indication.

Claim 37

A buffer integrated circuit as set forth in claim 31 including: a sixth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said first switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said first switch means; respective first switch control means corresponding to each said first switch means, for supplying a respective control bit thereto as causes that said first switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said sixth serial-in/parallel-out register output port being in a first rather than a second state; a seventh serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said second switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said second switch means; respective second switch control means corresponding to each said second switch means, for supplying a respective control bit thereto as causes that said second switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said seventh serial-in/parallel-out register output port is in a first rather than a second state; an eighth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said third switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said third switch means; respective third switch control means corresponding to each said third switch means, for supplying a respective control bit thereto as causes that said third switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said eighth serial-in/parallel-out register output port being in a first rather than a second state; a ninth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said fourth switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said fourth switch means; respective fourth switch control means corresponding to each said fourth switch means, for supplying a respective control bit thereto as causes that said fourth switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said ninth serial-in/parallel-out register output port is in a first rather than a second state; a tenth serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said fifth switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said fifth switch means; respective fifth switch control means corresponding to each said fifth switch means, for supplying a respective control bit thereto as causes that said fifth switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said tenth serial-in/parallel-out register output port being in a first rather than a second state; an eleventh serial-in/parallel-out register, having a serial input port connected from said test input terminal for receiving control bits for said sixth switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each said sixth switch means; respective sixth switch control means corresponding to each said sixth switch means, for supplying a respective control bit thereto as causes that said sixth switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said eleventh serial-in/parallel-out register output port is in a first rather than a second state; and means responsive to respective commands for supplying clocking signal to said first and second and third and fourth clocked bit latches, to said first serial-in/parallel-out register, to said second serial-in/parallel-out register, to each of said third and fourth and fifth serial-in/parallel-out registers, conditionally, to each of said sixth and eighth and tenth serial-in/parallel-out registers conditionally, to each of said seventh and ninth and eleventh serial-in/parallel-out registers conditionally, or to none of them.

Claim 38

A buffer integrated circuit as set forth in claim 35 wherein said means responsive to respective commands for supplying clocking signal includes therein: a decoder for determining which of said commands is supplied thereto via a set of instruction lines; means for generating clocking signal; means for applying clocking signal to said first and second and third and fourth clocked bit latches responsive to said command to supply clocking signal to said first and second and third and fourth clocked bit latches being received by said decoder; means for applying clocking signal to said first serial-in/parallel-out register responsive to a test output enable bit being stored in said fourth clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said first serial-in/parallel-out register; means for applying clocking signal to said second serial-in/parallel-out register responsive to a single-bit chip select signal being generated by said means for ORing said first, second and third input data port select bits at the same time said command to supply clocking signal to said second serial-in/parallel-out register is received by said decoder; means for applying clocking signal to said third serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said third and fourth and fifth serial-in/parallel-out registers conditionally; means for applying clocking signal to said fourth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said third and fourth and fifth serial-in/parallel-out registers conditionally; means for applying clocking signal to said fifth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said third and fourth and fifth serial-in/parallel-out registers conditionally; means for applying clocking signal to said sixth serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said sixth and eighth and tenth serial-in/parallel-out registers conditionally; means for applying clocking signal to said seventh serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said seventh and ninth and eleventh serial-in/parallel-out registers conditionally; means for applying clocking signal to said eighth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said sixth and eighth and tenth serial-in/parallel-out registers conditionally; means for applying clocking signal to said ninth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said seventh and ninth and eleventh serial-in/parallel-out registers conditionally; means for applying clocking signal to said tenth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said sixth and eighth and tenth serial-in/parallel-out registers conditionally; and means for applying clocking signal to said eleventh serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said seventh and ninth and eleventh serial-in/parallel-out registers conditionally.

Claim 39

A buffer integrated circuit as set forth in claim 35 including: respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively at the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; and means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response.

Claim 40

A buffer integrated circuit as set forth in claim 37 including: means for ANDing said first bit-error OR response and said first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and said second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and said third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a buffer integrated circuit fault indication.

Claim 41

A multiplicity of buffer integrated circuits as set forth in claim 38 connecting together groups of integrated circuits of the same type as each other, to form a fault-tolerant electronic system for use with a routing computer that responds to any circuit fault indications from said buffer integrated circuits to attempt to condition said buffer integrated circuits for interconnecting said integrated circuits of other type to provide at least one data path through said fault-tolerant electronic system.

Claim 42

A buffer integrated circuit as set forth in claim including: means responsive to a further command for conditionally supplying clocking signal to each of said third, fourth and fifth serial-in/parallel-out registers and at the same time conditioning said third, fourth and fifth serial-in/parallel-out registers each for responding to clocking signal supplied thereto to circulate the test vectors stored therein.

Claim 43

A buffer integrated circuit as set forth in claim 40 wherein said means responsive to respective commands and said means responsive to a further command together include: a decoder for determining which of said commands is supplied thereto via a set of instruction lines; means for generating clocking signal; means for applying clocking signal to said first and second and third and fourth clocked bit latches responsive to said command to supply clocking signal to said first and second and third and fourth clocked bit latches being received by said decoder; means for applying clocking signal to said first serial-in/parallel-out register responsive to a test output enable bit being stored in said fourth clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said first serial-in/parallel-out register; means for applying clocking signal to said second serial-in/parallel-out register responsive to a single-bit chip select signal being generated by said means for ORing said first, second and third input data port select bits at the same time said command to supply clocking signal to said second serial-in/parallel-out register is received by said decoder; means for applying clocking signal to said third serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said third and fourth and fifth serial-in/parallel-out registers conditionally; means for applying clocking signal to said fourth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said third and fourth and fifth serial-in/parallel-out registers conditionally; means for applying clocking signal to said fifth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said third and fourth and fifth serial-in/parallel-out registers conditionally; means for applying clocking signal to said sixth serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said sixth and eighth and tenth serial-in/parallel-out registers conditionally; means for applying clocking signal to said seventh serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said seventh and ninth and eleventh serial-in/parallel-out registers conditionally; means for applying clocking signal to said eighth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said sixth and eighth and tenth serial-in/parallel-out registers conditionally; means for applying clocking signal to said ninth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said seventh and ninth and eleventh serial-in/parallel-out registers conditionally; means for applying clocking signal to said tenth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said sixth and eighth and tenth serial-in/parallel-out registers conditionally; and means for applying clocking signal to said eleventh serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said seventh and ninth and eleventh serial-in/parallel-out registers conditionally.

Claim 44

A buffer integrated circuit as set forth in claim 41 including: respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively at the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; and means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response.

Claim 45

A buffer integrated circuit as set forth in claim 42 including: means for ANDing said first bit-error OR response and said first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and said second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and said third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a buffer integrated circuit fault indication.

Claim 46

A multiplicity of buffer integrated circuits as set forth in claim 43 connecting together groups of integrated circuits of the same type as each other, to form a fault-tolerant electronic system for use with a routing computer that responds to any circuit fault indications from said buffer integrated circuits to attempt to condition said buffer integrated circuits for interconnecting said integrated circuits of other type to provide at least one data path through said fault-tolerant electronic system.

Claim 47

A buffer integrated circuit as set forth in claim 31 including: a sixth serial-in/parallel-out register having a serial input port connected from said test input terminal for receiving control bits for each said first switch means and each said second switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each of said first switch means and said second switch means; respective first switch control means corresponding to each said first switch means, for supplying a respective control bit thereto as causes that said first switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said sixth serial-in/parallel-out register output port being in a first rather than a second state; respective second switch control means corresponding to each said second switch means, for supplying a respective control bit thereto as causes that said second switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said sixth serial-in/parallel-out register output port is in a first rather than a second state; a seventh serial-in/parallel-out register having a serial input port connected from said test input terminal for receiving control bits for each said third switch means and each said fourth switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each of said third switch means and said fourth switch means; respective third switch control means corresponding to each said third switch means, for supplying a respective control bit thereto as causes that said third switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said seventh serial-in/parallel-out register output port being in a first rather than a second state; respective fourth switch control means corresponding to each said fourth switch means, for supplying a respective control bit thereto as causes that said fourth switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said seventh serial-in/parallel-out register output port is in a first rather than a second state; an eighth serial-in/parallel-out register having a serial input port connected from said test input terminal for receiving control bits for each said fifth switch means and each said sixth switch means one bit at a time during selective clocking of that register, and having a parallel output port with a respective bit place corresponding to each of said fifth switch means and said sixth switch means; respective fifth switch control means corresponding to each said fifth switch means, for supplying a respective control bit thereto as causes that said fifth switch means to selectively connect, responsive to said test enable terminal not receiving said test enable bit or the corresponding bit place of said eighth serial-in/parallel-out register output port being in a first rather than a second state; respective sixth switch control means corresponding to each said sixth switch means, for supplying a respective control bit thereto as causes that said sixth switch means to selectively connect, responsive to said test enable terminal receiving said test enable bit at the same time the corresponding bit place of said eighth serial-in/parallel-out register output port is in a first rather than a second state; and means responsive to respective commands for supplying clocking signal to said first and second and third and fourth clocked bit latches, to said first serial-in/parallel-out register, to said second serial-in/parallel-out register to each of said third and fourth and fifth serial-in/parallel-out registers conditionally, to each of said sixth and seventh and eighth serial-in/parallel-out registers conditionally, or to none of them.

Claim 48

A buffer integrated circuit as set forth in claim 45 wherein said means responsive to respective commands for supplying clocking signal includes therein: a decoder for determining which of said commands is supplied thereto via a set of instruction lines; means for generating clocking signal; means for applying clocking signal to said first and second and third and fourth clocked bit latches responsive to said command to supply clocking signal to said first and second and third and fourth clocked bit latches being received by said decoder; means for applying clocking signal to said first serial-in/parallel-out register responsive to a test output enable bit being stored in said fourth clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said first serial-in/parallel-out register; means for applying clocking signal to said second serial-in/parallel-out register responsive to a single-bit chip select signal being generated by said means for ORing said first, second and third input data port select bits at the same time said command to supply clocking signal to said second serial-in/parallel-out register is received by said decoder; means for applying clocking signal to said third serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said third and fourth and fifth serial-in/parallel-out registers conditionally; means for applying clocking signal to said fourth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said third and fourth and fifth serial-in/parallel-out registers conditionally; means for applying clocking signal to said fifth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said third and fourth and fifth serial-in/parallel-out registers conditionally; means for applying clocking signal to said sixth serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said sixth and seventh and eighth serial-in/parallel-out registers conditionally; means for applying clocking signal to said seventh serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said sixth and seventh and eighth serial-in/parallel-out registers conditionally; and means for applying clocking signal to said eighth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said sixth and seventh and eighth serial-in/parallel-out registers conditionally.

Claim 49

A buffer integrated circuit as set forth in claim 46 including: respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively at the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; and means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response.

Claim 50

A buffer integrated circuit as set forth in claim 47 including: means for ANDing said first bit-error OR response and said first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and said second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and said third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a buffer integrated circuit fault indication.

Claim 51

A multiplicity of buffer integrated circuits as set forth in claim 48 connecting together groups of integrated circuits of the same type as each other, to form a fault-tolerant electronic system for use with a routing computer that responds to any circuit fault indications from said buffer integrated circuits to attempt to condition said buffer integrated circuits for interconnecting said integrated circuits of other type to provide at least one data path through said fault-tolerant electronic system.

Claim 52

A buffer integrated circuit as set forth in claim 45 including: means responsive to a further command for conditionally supplying clocking signal to each of said third, fourth and fifth serial-in/parallel-out registers and at the same time conditioning said third, fourth and fifth serial-in/parallel-out registers each for responding to clocking signal supplied thereto to circulate the test vectors stored therein.

Claim 53

A buffer integrated circuit as set forth in claim 50 wherein said means responsive to respective commands for supplying clocking signal includes therein: a decoder for determining which of said commands is supplied thereto via a set of instruction lines; means for generating clocking signal; means for applying clocking signal to said first and second and third and fourth clocked bit latches responsive to said command to supply clocking signal to said first and second and third and fourth clocked bit latches being received by said decoder; means for applying clocking signal to said first serial-in/parallel-out register responsive to a test output enable bit being stored in said fourth clocked bit latch and to said decoder at the same time receiving said command to supply clocking signal to said first serial-in/parallel-out register; means for applying clocking signal to said second serial-in/parallel-out register responsive to a single-bit chip select signal being generated by said means for ORing said first, second and third input data port select bits at the same time said command to supply clocking signal to said second serial-in/parallel-out register is received by said decoder; means for applying clocking signal to said third serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said third and fourth and fifth serial-in/parallel-out registers conditionally; means for applying clocking signal to said fourth serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said third and fourth and fifth serial-in/parallel-out registers conditionally; means for applying clocking signal to said fifth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said third and fourth and fifth serial-in/parallel-out registers conditionally; means for applying clocking signal to said sixth serial-in/parallel-out register responsive to the simultaneous occurrences of said first input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said sixth and seventh and eighth serial-in/parallel-out registers conditionally; means for applying clocking signal to said seventh serial-in/parallel-out register responsive to the simultaneous occurrences of said second input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said sixth and seventh and eighth serial-in/parallel-out registers conditionally; and means for applying clocking signal to said eighth serial-in/parallel-out register responsive to the simultaneous occurrences of said third input enable signal being generated and said decoder receiving said command to supply clocking signal to each of said sixth and seventh and eighth serial-in/parallel-out registers conditionally.

Claim 54

A buffer integrated circuit as set forth in claim 51 including: respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively at the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; and means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response.

Claim 55

A buffer integrated circuit as set forth in claim 52 including: means for ANDing said first bit-error OR response and said first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and said second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and said third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a buffer integrated circuit fault indication.

Claim 56

A multiplicity of buffer integrated circuits as set forth in claim 53 connecting together groups of integrated circuits of the same type as each other, to form a fault-tolerant electronic system for use with a routing computer that responds to any circuit fault indications from said buffer integrated circuits to attempt to condition said buffer integrated circuits for interconnecting said integrated circuits of other type to provide at least one data path through said fault-tolerant electronic system.

Claim 57

An integrated circuit comprising: a serial data input terminal; a chip select input terminal; a chip select output terminal; means for generating clocking signal; a clocked bit latch in connection between said chip select input terminal and said chip select output terminal for storing a chip select bit as may be received through said chip select input terminal during selective application of said clocking signal to said clocked bit latch; a plurality of serial-in/parallel-out registers, each having a respective serial input port for loading data therethrough from said serial data input terminal one bit at a time during selective application of said clocking signal to that register and having a respective parallel output port; a decoder for decoding a plurality of commands received in coded form to generate corresponding one-bit decoder results; means responsive to the one-bit decoder result corresponding to a first of said commands for applying said clocking signal to said clocked bit latch; means responsive to the one-bit decoder result corresponding to a second of said commands for applying said clocking signal to a first of said plurality of serial-in/parallel-out registers, for shifting a register select token bit from said serial data input terminal within said first serial-in/parallel-out register to appear at a bit place in its parallel output port, which said first serial-in/parallel-out register has a respective bit place in its parallel output port corresponding to each of the remaining ones of said plurality of serial-in/parallel-out registers; and respective means corresponding to each remaining one of said plurality of serial-in/parallel-out registers for applying said clocking signal thereto, responsive to the one-bit decoder result corresponding to a third of said commands appearing concurrently with a register select token bit being in the corresponding bit place of the parallel output port of said first serial-in/parallel-out register.

Claim 58

An integrated circuit comprising: a serial data input terminal; a chip select input terminal; a chip select output terminal; means for generating clocking signal; a clocked bit latch in connection between said chip select input terminal and said chip select output terminal for storing a chip select bit as may be received through said chip select input terminal during selective application of said clocking signal to said clocked bit latch; a plurality of serial-in/parallel-out registers, each having a respective serial input port for loading data therethrough from said serial data input terminal one bit at a time during selective application of said clocking signal to that register and having a respective parallel output port; a decoder for decoding a plurality of commands received in coded form to generate corresponding one-bit decoder results; means responsive to the one-bit decoder result corresponding to a first of said commands for applying said clocking signal to said clocked bit latch; means responsive to the one-bit decoder result corresponding to a second of said commands for applying said clocking signal to a first of said plurality of serial-in/parallel-out registers, for shifting a register select token bit from said serial data input terminal within said first serial-in/parallel-out register to appear at a bit place in its parallel output port, which said first serial-in/parallel-out register has a respective bit place in its parallel output port corresponding to each of the remaining ones of said plurality of serial-in/parallel-out registers; and respective means corresponding to each remaining one of said plurality of serial-in/parallel-out registers for applying said clocking signal thereto, responsive to the one-bit decoder result corresponding to a third of said commands appearing concurrently with a register select token bit being in the corresponding bit place of the parallel output port of said first serial-in/parallel-out register.

Claim 59

In combination: a first plurality of tristate drivers, N in number, each having a respective data bit input terminal, a respective control bit input terminal and a respective data bit output terminal, which data bit output terminals together form a data output port for said integrated circuit; a voter circuit of the type performing majority logic on a bit-sliced basis, said voter circuit having first, second and third input ports and having an output port, each of which ports has N respective bit places therein, the N respective bit places of the output port of said voter circuit supplying respective ones of data bits applied to the data bit terminals of said first plurality of tristate drivers; respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively at the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response; means for ANDing said first bit-error OR response and a first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and a second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and a third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a circuit fault indication.

Claim 60

In combination: a first plurality of tristate drivers, N in number, each having a respective data bit input terminal, a respective control bit input terminal and a respective data bit output terminal, which data bit output terminals together form a data output port for said integrated circuit; a voter circuit of the type performing majority logic on a bit-sliced basis, said voter circuit having first, second and third input ports and having an output port, each of which ports has N respective bit places therein, the N respective bit places of the output port of said voter circuit supplying respective ones of data bits applied to the data bit terminals of said first plurality of tristate drivers; respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively at the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response; means for ANDing said first bit-error OR response and a first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and a second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and a third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a circuit fault indication.

Claim 61

A buffer integrated circuit providing a testing interface, said buffer integrated circuit being arranged in combination with said first, second and third data processing circuits of similar type, having respective input ports connected for receiving the same input signal and having respective output ports, each of which output ports has N respective bit places therein, N being an integer greater than one, wherein said buffer integrated circuit further includes: a first plurality of tristate drivers, N in number, each having a respective data bit input terminal, a respective control bit input terminal and a respective data output terminal, which data bit input terminals together form a data input port for said buffer integrated circuit, and which data bit output terminals together form a data output port for said buffer integrated circuit; means for applying data signal bits to the data bit input terminals of said first plurality of tristate drivers; means for applying respective control signal bits to the control bit input terminals of said first plurality of tristate drivers; a test output terminal; multiplexer means for selecting to said test output terminal the respective logic condition at any one of the data bit output terminals of said first plurality of tristate drivers; a voter circuit of the type performing majority logic on a bit-sliced basis, said voter circuit having first, second and third input ports and having an output port, each of which ports has N respective bit places therein, the N respective bit places of the output port of said voter circuit supplying respective ones of data bits applied to the data bit terminals of said first plurality of tristate drivers; respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively from the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response; means responsive to a first input enable signal for selectively connecting the output port of said first data processing circuit to the first input port of said voter circuit; means responsive to a second input enable signal for selectively connecting the output port of said second data processing circuit to the second input port of said voter circuit; means responsive to a third input enable signal for selectively connecting the output port of said third data processing circuit to the third input port of said voter circuit; means for ANDing said first bit-error OR response and said first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and a second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and a third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a circuit fault indication.

Claim 62

A buffer integrated circuit providing a testing interface, said buffer integrated circuit being arranged in combination with said first, second and third data processing circuits of similar type, having respective input ports connected for receiving the same input signal and having respective output ports, each of which output ports has N respective bit places therein, N being an integer greater than one, wherein said buffer integrated circuit further includes: a first plurality of tristate drivers, N in number, each having a respective data bit input terminal, a respective control bit input terminal and a respective data output terminal, which data bit input terminals together form a data input port for said buffer integrated circuit, and which data bit output terminals together form a data output port for said buffer integrated circuit; means for applying data signal bits to the data bit input terminals of said first plurality of tristate drivers; means for applying respective control signal bits to the control bit input terminals of said first plurality of tristate drivers; a test output terminal; multiplexer means for selecting to said test output terminal the respective logic condition at any one of the data bit output terminals of said first plurality of tristate drivers; a voter circuit of the type performing majority logic on a bit-sliced basis, said voter circuit having first, second and third input ports and having an output port, each of which ports has N respective bit places therein, the N respective bit places of the output port of said voter circuit supplying respective ones of data bits applied to the data bit terminals of said first plurality of tristate drivers; respective first, second and third bit-error detectors associated with each bit slice of said voter circuit responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively from the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a first bit-error OR response; means for ORing error indications from said second bit-error detectors to generate a second bit-error OR response; means for ORing error indications from said third bit-error detectors to generate a third bit-error OR response; means responsive to a first input enable signal for selectively connecting the output port of said first data processing circuit to the first input port of said voter circuit; means responsive to a second input enable signal for selectively connecting the output port of said second data processing circuit to the second input port of said voter circuit; means responsive to a third input enable signal for selectively connecting the output port of said third data processing circuit to the third input port of said voter circuit; means for ANDing said first bit-error OR response and said first input enable signal to generate a first AND response; means for ANDing said second bit-error OR response and a second input enable signal to generate a second AND response; means for ANDing said third bit-error OR response and a third input enable signal to generate a third AND response; and means for ORing said first AND response, said second AND response, and said third AND response to generate a circuit fault indication.

Claim 63

A combination as set forth in claim 57 operated so as to apply a prescribed pattern of said first, second and third input enable signals thereto as long as said circuit fault indication is not generated; and when said circuit fault indication is generated changing in a prescribed manner said prescribed pattern of said first, second and third input enable signals applied thereto until said circuit fault indication is not generated.

Claim 64

In combination: a voter circuit of the type performing majority logic on a bit-sliced basis, said voter circuit having first, second and third input ports connected at least, said voter circuit having an output port, each of which ports of said voter circuit has N respective bit places therein, N being an integer greater than one; first, second and third data processing circuits of the same type, having respective input ports connected for receiving the same input signal and having respective output ports, each of which output ports has N respective bit places therein; means for applying, at least at selected times, a signal from the output port of said first data processing circuit to the first input port of said voter circuit and being of a type for selectively applying the signal from the output port of said first data processing circuit to the first input port of said voter circuit in response to a first input enable signal; means for applying, at least at selected times, a signal from the output port of said second data processing circuit to the first input port of said voter circuit and being of a type for selectively applying the signal from the output port of said second data processing circuit to the second input port of said voter circuit in response to a second input enable signal; means for applying, at least at selected times, a signal from the output port of said third data processing circuit to the third input port of said voter circuit and being of a type for selectively applying the signal from the output port of said third data processing circuit to the third input port of said voter circuit in response to a third input enable signal; respective first, second and third bit-error detectors associated with each bit slice of said voter circuit for responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively at the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a signal indicative of a likelihood of fault in said first data processing circuit; means for ORing error indications from said second bit-error detectors to generate a signal indicative of a likelihood of fault in said second data processing circuit; means for ORing error indications from said third bit-error detectors to generate a signal indicative of a likelihood of fault in said third data processing circuit; and means for responding to any of said signals indicative of a likelihood of fault being generated to generate an indication of a fault in at least one of said first, second and third data processing circuits, and comprising: means for ANDing said first enable signal and said signal indicative of a likelihood of fault in said first data processing circuit to generate a first AND response; means for ANDing said second enable signal and said signal indicative of a likelihood of fault in said second data processing circuit to generate a second AND response; means for ANDing said third enable signal and said signal indicative of a likelihood of fault in said third data processing circuit to generate a third AND response; means for ORing said first AND response, said second AND response, and said third AND response to generate said indication of a fault in at least one of said first, second and third data processing circuits.

Claim 65

In combination: a voter circuit of the type performing majority logic on a bit-sliced basis, said voter circuit having first, second and third input ports connected at least, said voter circuit having an output port, each of which ports of said voter circuit has N respective bit places therein, N being an integer greater than one; first, second and third data processing circuits of the same type, having respective input ports connected for receiving the same input signal and having respective output ports, each of which output ports has N respective bit places therein; means for applying, at least at selected times, a signal from the output port of said first data processing circuit to the first input port of said voter circuit and being of a type for selectively applying the signal from the output port of said first data processing circuit to the first input port of said voter circuit in response to a first input enable signal; means for applying, at least at selected times, a signal from the output port of said second data processing circuit to the first input port of said voter circuit and being of a type for selectively applying the signal from the output port of said second data processing circuit to the second input port of said voter circuit in response to a second input enable signal; means for applying, at least at selected times, a signal from the output port of said third data processing circuit to the third input port of said voter circuit and being of a type for selectively applying the signal from the output port of said third data processing circuit to the third input port of said voter circuit in response to a third input enable signal; respective first, second and third bit-error detectors associated with each bit slice of said voter circuit for responding to any differences between the bit that bit slice supplies to the output port of said voter circuit and the bits that bit slice receives respectively at the first, second and third input ports of said voter circuit for generating respective error indications; means for ORing error indications from said first bit-error detectors to generate a signal indicative of a likelihood of fault in said first data processing circuit; means for ORing error indications from said second bit-error detectors to generate a signal indicative of a likelihood of fault in said second data processing circuit; means for ORing error indications from said third bit-error detectors to generate a signal indicative of a likelihood of fault in said third data processing circuit; and means for responding to any of said signals indicative of a likelihood of fault being generated to generate an indication of a fault in at least one of said first, second and third data processing circuits, and comprising: means for ANDing said first enable signal and said signal indicative of a likelihood of fault in said first data processing circuit to generate a first AND response; means for ANDing said second enable signal and said signal indicative of a likelihood of fault in said second data processing circuit to generate a second AND response; means for ANDing said third enable signal and said signal indicative of a likelihood of fault in said third data processing circuit to generate a third AND response; means for ORing said first AND response, said second AND response, and said third AND response to generate said indication of a fault in at least one of said first, second and third data processing circuits.

Claim 66

A combination as set forth in claim 59 operated so as to apply a prescribed pattern of said first, second and third input enable signals thereto as long as said indication of a fault in at least one of said first, second and third data processing circuits is not generated; and when said indication of a fault in at least one of said first, second and third data processing circuits is generated changing in a prescribed manner said prescribed pattern of said first, second and third input enable signals applied thereto until said indication of a fault in at least one of said first, second and third data processing circuits is not generated.