US4490673A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Testing an integrated circuit containing a tristate driver and a control signal generating network therefor
Assignee: International Business Machines Corp
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Filing: 1982-05-26
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Granted: 1984-12-25
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Expires: 2002-05-26
Abstract
Abstract An integrated circuit chip includes a tristate driver which assumes an active logical state in response to a data signal at its data input and assumes a high impedance state in response to a control signal at its control input. The integrated circuit chip also includes a control signal generating network which is connected to the tristate driver's control input for producing the control signal. The control signal generating network may be tested by connecting the control signal generating network to the data input and overriding the control input to prevent the tristate driver from assuming the high impedance state. Thus, for testing purposes, the proper response of the control signal generating circuit may be ascertained by monitoring the active state of the tristate driver.
Inventors
- 👤 Arnold Blum
- 👤 Helmut Schettler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:47
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/316
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
148 words
In an integrated circuit which includes a tristate driver having data and control inputs, said tristate driver assuming an active logical state in response to a data signal at said data input, and assuming a high impedance state in response to a control signal at said control input, said integrated circuit further including a control signal generating network which is connected to said control input for producing said control signal; apparatus for testing said control signal generating network, comprising: means for connecting said control signal generating network to said data input so that said tristate driver may assume an active logical state in response to said control signal generating network; and overriding means connected to said control input for preventing said tristate driver from assuming the high impedance state; whereby said control signal generating network may be tested by monitoring the active logical state of said tristate driver.
Claim 2
Dependent Claim
148 words
In an integrated circuit which includes a tristate driver having data and control inputs, said tristate driver assuming an active logical state in response to a data signal at said data input, and assuming a high impedance state in response to a control signal at said control input, said integrated circuit further including a control signal generating network which is connected to said control input for producing said control signal; apparatus for testing said control signal generating network, comprising: means for connecting said control signal generating network to said data input so that said tristate driver may assume an active logical state in response to said control signal generating network; and overriding means connected to said control input for preventing said tristate driver from assuming the high impedance state; whereby said control signal generating network may be tested by monitoring the active logical state of said tristate driver.
Claim 3
Dependent Claim
25 words
The apparatus of claim 1 further comprising: second overriding means connected to said control input, for forcing said tristate driver into the high impedance state.
Claim 4
Dependent Claim
36 words
The apparatus of claim 1 wherein said connecting means comprises a logic gate, the output of which is connected to said data input, and one input of which is connected to said control signal generating network.
Claim 5
Dependent Claim
13 words
The apparatus of claim 3 wherein said logic gate is an OR gate.
Claim 6
Dependent Claim
19 words
The apparatus of claim 3 further comprising a replacement data input connected to another input of said logic gate.
Claim 7
Dependent Claim
37 words
The apparatus of claim 2 wherein said second overriding means comprises a logic gate, the output of which is connected to said control input and one input of which is connected to said control signal generating network.
Claim 8
Dependent Claim
13 words
The apparatus of claim 6 wherein said logic gate is an OR gate.
Claim 9
Dependent Claim
15 words
The apparatus of claim 1 wherein said control signal generating network is a combinational network.
Claim 10
Dependent Claim
149 words
In an integrated circuit which includes a tristate driver having data and control inputs, said tristate driver assuming an active logical state in response to a data signal at said data input, and assuming a high impedance state in response to a control signal at said control input, said integrated circuit further including a control signal generating network, the output of which is connected to said control input for producing said control signal; a method for testing said control signal generating network comprising the steps of: connecting said control signal generating network to said data input so that said tristate driver assumes an active logical state in response to said control signal generating network; and overriding said control input to prevent said tristate driver from assuming the high impedance state; whereby said control signal generating network may be tested by monitoring the active logical state of said tristate driver.
Claim 11
Dependent Claim
149 words
In an integrated circuit which includes a tristate driver having data and control inputs, said tristate driver assuming an active logical state in response to a data signal at said data input, and assuming a high impedance state in response to a control signal at said control input, said integrated circuit further including a control signal generating network, the output of which is connected to said control input for producing said control signal; a method for testing said control signal generating network comprising the steps of: connecting said control signal generating network to said data input so that said tristate driver assumes an active logical state in response to said control signal generating network; and overriding said control input to prevent said tristate driver from assuming the high impedance state; whereby said control signal generating network may be tested by monitoring the active logical state of said tristate driver.
Claim 12
Dependent Claim
29 words
The method of claim 9 wherein said connecting step is preceded by the step of overriding said control input to force said tristate driver into the high impedance state.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-25 | 1988-06-25 | 1988-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-25 | 1992-06-25 | 1992-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-25 | 1996-06-25 | 1996-12-25 | $7700.00 | Window Closed / Lapsed |