Circuit including bistable, bipolar transistor

Claim 1

A circuit, comprising at least one bipolar transistor comprising an emitter, a base, and a collector, and electrical contacts to, respectively, the emitter and collector, adapted for applying a voltage between the emitter and the collector, wherein: a) the emitter includes a first semiconductor region of a first conductivity type, the region having first majority carriers that are electrons if the first conductivity type is n type and holes if the first conductivity type is p type; b) the base includes a second semiconductor region of a second conductivity type opposite to the first conductivity type; c) the collector includes third and fourth semiconductor regions and between the third and fourth regions, at least a fifth semiconductor region, the base being positioned between the emitter and collector such that the base is adjacent to the third semiconductor region: d) the collector is capable of receiving electrical charges emitted by the emitter and transported across the base; e) each of the second, third, fourth, and fifth semiconductor regions has an energy band for said first majority carriers, said energy band being a conduction band if the first majority carriers are electrons and a valence band if the first majority carriers are holes, each band further having a band edge; and in the absence of applied voltages, the band edge of the fifth semiconductor region lies at a lower energy of first majority carriers than the band edges of the third and fourth regions; CHARACTERIZED IN THAT the third semiconductor region is of the first conductivity type; and the compositions of the third, fourth, and fifth semiconductor regions are selected such that at room temperature and in the absence of applied voltages, the band edge of the third region corresponds to an energy of first majority carriers at least 1.5 kT greater than the band edges of the second and fifth regions, and the band edge of the fourth region corresponds to an energy of first majority carriers at least 1.5 kT greater than the band edge of the fifth region, such that the third semiconductor region constitutes a potential barrier to the flow of electrical charges from the base to the collector, and the fourth semiconductor region constitutes a potential barrier to the flow of electrical charges across the collector.