US5151376A
Expired / Lapsed
US
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Method of making polycrystalline silicon resistors for integrated circuits
Assignee: STMicroelectronics lnc USA
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Filing: 1990-05-31
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Granted: 1992-09-29
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Expires: 2010-05-31
Abstract
Abstract A method for fabricating polycrystalline silicon resistor structures includes steps directed to the provision of a polycrystalline silicon structure having a decreased width. In one embodiment, sidewall spacers are used to narrow a region in which the polycrystalline silicon resistors are formed. In an alternative embodiment, polycrystalline silicon resistors are formed as sidewall structures in a resistor region. Use of either technique provides a reduced cross-section for the resistor structures, allowing shorter resistors to be used, or providing increased resistance for longer resistors.
Inventors
- 👤 Charles R. Spinner, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:43
CPC Classifications
H; H10; H10D; H10D84/00; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
119 words
A method for fabricating a resistor structure between first and second laterally spaced regions in an integrated circuit device, comprising the steps of: forming a first insulating layer over the device; patterning the first insulating layer to define an elongate region between the first and second laterally spaced regions for formation of the resistor structure; forming a second insulating layer over the device; anisotropically etching the second insulating layer, leaving insulating sidewalls in the elongate region, wherein a narrowed region is defined; depositing a layer of polycrystalline silicon over the device; and anistropically etching the polycrystalline silicon layer, wherein polycrystalline silicon remains in the narrowed region to form the resistor structure connecting the first and second laterally spaced regions.
Claim 2
Independent Claim
119 words
A method for fabricating a resistor structure between first and second laterally spaced regions in an integrated circuit device, comprising the steps of: forming a first insulating layer over the device; patterning the first insulating layer to define an elongate region between the first and second laterally spaced regions for formation of the resistor structure; forming a second insulating layer over the device; anisotropically etching the second insulating layer, leaving insulating sidewalls in the elongate region, wherein a narrowed region is defined; depositing a layer of polycrystalline silicon over the device; and anistropically etching the polycrystalline silicon layer, wherein polycrystalline silicon remains in the narrowed region to form the resistor structure connecting the first and second laterally spaced regions.
Claim 3
Dependent Claim
52 words
The method of claim 1, further comprising the step of: before said polycrystalline silicon etching step, masking portions of the polycrystalline silicon layer to protect selected regions thereof, leaving the narrowed region unmasked, wherein the selected regions of the polycrystalline silicon layer will not be etched during the polycrystalline silicon etching step.
Claim 4
Dependent Claim
43 words
The method of claim 2, further comprising the step of: before said polycrystalline silicon deposition step, etching contacts to underlying circuit structures, wherein the contacts will be masked so as to be included in the protected selected regions of the polycrystalline silicon layer.
Claim 5
Dependent Claim
13 words
The method of claim 1, wherein the first insulating layer comprises silicon nitride.
Claim 6
Dependent Claim
14 words
The method of claim 1, wherein the second insulating layer comprises a deposited oxide.
Claim 7
Dependent Claim
26 words
The method of claim 1, further comprising the step of: prior to said first insulating layer forming step, planarizing a surface of the integrated circuit device.
Claim 8
Dependent Claim
42 words
The method of claim 6, wherein said planarizing step comprises the steps of: depositing a layer of reflowable glass over the device; and heating the device to a temperature sufficient to cause the glass layer to flow into a relatively planar layer.
Claim 9
Dependent Claim
11 words
The method of claim 7, wherein the reflowable glass comprises BPSG.
Claim 10
Independent Claim
81 words
A method for fabricating a resistor structure in an integrated circuit device, comprising the steps of: forming a first insulating layer over the device; patterning the first insulating layer to define an elongate region for formation of the resistor structure, wherein such elongate region has substantially vertical side walls; depositing a layer of polycrystalline silicon over the device; and anisotropically etching the polycrystalline silicon layer, wherein polycrystalline silicon side wall regions remain in the elongate region to form the resistor structure.
Claim 11
Independent Claim
81 words
A method for fabricating a resistor structure in an integrated circuit device, comprising the steps of: forming a first insulating layer over the device; patterning the first insulating layer to define an elongate region for formation of the resistor structure, wherein such elongate region has substantially vertical side walls; depositing a layer of polycrystalline silicon over the device; and anisotropically etching the polycrystalline silicon layer, wherein polycrystalline silicon side wall regions remain in the elongate region to form the resistor structure.
Claim 12
Dependent Claim
52 words
The method of claim 9, further comprising the step of: before said polycrystalline silicon etching step, masking portions of the polycrystalline silicon layer to protect selected regions thereof, leaving the elongate region unmasked wherein the selected regions of the polycrystalline silicon layer will not be etched during the polycrystalline silicon etching step.
Claim 13
Dependent Claim
43 words
The method of claim 10, further comprising the step of: before said polycrystalline silicon deposition step, etching contacts to underlying circuit structures, wherein the contacts will be masked so as to be included in the protected selected regions of the polycrystalline silicon layer.
Claim 14
Dependent Claim
13 words
The method of claim 9, wherein the first insulating layer comprisess silicon nitride.
Claim 15
Dependent Claim
26 words
The method of claim 9, further comprising the step of: prior to said first insulating layer forming step, planarizing a surface of the integrated circuit device.
Claim 16
Dependent Claim
42 words
The method of claim 13, wherein said planarizing step comprises the steps of: depositing a layer of reflowable glass over the device; and heating the device to a temperature sufficient to cause the glass layer to flow into a relatively planar layer.
Claim 17
Dependent Claim
11 words
The method of claim 14, wherein the reflowable glass comprises BPSG.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-29 | 1996-03-30 | 1996-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-29 | 2000-03-30 | 2000-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-29 | 2004-03-30 | 2004-09-29 | $7700.00 | Window Closed / Lapsed |