US5144570A
Expired / Lapsed
US
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Normalization estimator
Assignee: National Semiconductor Corp
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Filing: 1991-06-17
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Granted: 1992-09-01
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Expires: 2011-06-17
Abstract
Abstract A normalization circuit (24) which comprises a signed digit subtracter (25) coupled to operand registers (14, 19). The signed digit subtracter (25) subtracts the operands and inputs a signed digit difference to a pseudovalue converter (27). The pseudovalue converter (27) generates a pseudovalue in non-redundant format which contains its most significant non-zero bit in the selected bit position. The pseudovalue is output to a leading zero counter (28) which counts the number of leading zeroes in the pseudovalue.
Inventors
- 👤 Robert D. Maher, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:19
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F5/00; G06F5/01; G06F5/012
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
88 words
A normalization circuit for normalizing a result of an arithmetic operation performed on a first and second operands by a computational circuit, comprising: a signed digit subtracter operable to subtract the first operand from the second operand, and output a difference; a pseudovalue converter having an input coupled to said output of said signed digit subtracter, said pseudovalue converter operable to convert said difference into pseudovalue; and a leading zero counter coupled to receive said pseudovalue and operable to count the number of leading zeroes in said pseudovalue.
Claim 2
Dependent Claim
88 words
A normalization circuit for normalizing a result of an arithmetic operation performed on a first and second operands by a computational circuit, comprising: a signed digit subtracter operable to subtract the first operand from the second operand, and output a difference; a pseudovalue converter having an input coupled to said output of said signed digit subtracter, said pseudovalue converter operable to convert said difference into pseudovalue; and a leading zero counter coupled to receive said pseudovalue and operable to count the number of leading zeroes in said pseudovalue.
Claim 3
Dependent Claim
18 words
The normalization circuit of claim 1 wherein said normalization circuit is coupled in parallel with said computational circuit.
Claim 4
Dependent Claim
44 words
The normalization circuit of claim 1 wherein said pseudovalue converter is operable to generate said pseudovalue such that said pseudovalue contains a number of leading zeroes equal to or one less than the number of leading zeroes in said result of said arithmetic operation.
Claim 5
Dependent Claim
42 words
The normalization circuit of claim 1 wherein said pseudovalue converter is operable to perform a three bit overlapped scan on said difference to identify predetermined three bit patterns indicative of the approximate location of the most significant nonzero bit in said result.
Claim 6
Dependent Claim
12 words
The normalization circuit of claim 1 wherein the arithmetic operation comprises subtraction.
Claim 7
Dependent Claim
29 words
The normalization circuit of claim 1 wherein one of the operands is selectively denormalized prior to performing the arithmetic operation such that exponents associated with the operands are equal.
Claim 8
Independent Claim
117 words
A method of normalizing a result of an arithmetic operation of two floating point operands comprising the steps of: performing a signed digit subtraction on said floating point operands to yield a signed digit difference in a signed digit subtractor; transmitting signals associated with the signed digit difference to a pseudovalue converter; converting the signed digit difference to a non-redundant pseudovalue having a number of zeroes within a predetermined range of the number of zeroes in the result of the arithmetic operation in the pseudovalue converter; and counting the number of zeroes in the pseudovalue to yield an estimation of the number of leading zeroes in the results of the arithmetic operation in a leading zero counter.
Claim 9
Independent Claim
117 words
A method of normalizing a result of an arithmetic operation of two floating point operands comprising the steps of: performing a signed digit subtraction on said floating point operands to yield a signed digit difference in a signed digit subtractor; transmitting signals associated with the signed digit difference to a pseudovalue converter; converting the signed digit difference to a non-redundant pseudovalue having a number of zeroes within a predetermined range of the number of zeroes in the result of the arithmetic operation in the pseudovalue converter; and counting the number of zeroes in the pseudovalue to yield an estimation of the number of leading zeroes in the results of the arithmetic operation in a leading zero counter.
Claim 10
Dependent Claim
32 words
The method of claim 7, and further comprising the step of: shifting the result of the arithmetic operation a number of bit positions equal to the estimation to yield an intermediate result.
Claim 11
Dependent Claim
38 words
The method of claim 8 and further comprising the step of conditionally shifting the intermediate result a single bit position responsive to the state of the most significant bit in the intermediate result to yield a normalized result.
Claim 12
Dependent Claim
11 words
The method of claim 7 wherein the arithmetic operation comprises subtraction.
Claim 13
Dependent Claim
27 words
The method of claim 7 wherein one of the operands is denormalized prior to performing the arithmetic operation such that exponents associated with the operands are equal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-01 | 1996-03-02 | 1996-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-01 | 2000-03-02 | 2000-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-01 | 2004-03-02 | 2004-09-01 | $7700.00 | Window Closed / Lapsed |