US4878190A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Floating point/integer processor with divide and square root functions
Assignee: Texas Instruments Inc
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Filing: 1988-01-29
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Granted: 1989-10-31
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Expires: 2008-01-29
Abstract
Abstract A processor (10) operable to calculate division and square root functions comprises a multiplier (48) having a multiplier array (116), a pipeline register (50), a correction generator (122), and a converter/rounder (52). The products generated by the multiplier array (116) are fed back to the multiplier (48) to avoid delays associated with the remainder of the multiplier circuitry. The correction generator (122) which performs a subtraction of the product output form the multiplier array (116) from a constant, is disposed between the multiplier array (116) and the converter/rounder (52). Hence, the subtraction necessry to compute the next estimate may be performed in parallel with other multiplications, further reducing the time necessary to perform the calculation. Compare circuitry (120) is operable to compare the final approximation with an operand to quickly determine the direction of rounding.
Inventors
- 👤 Henry M. Darley
- 👤 Michael C. Gill
- 👤 Dale C. Earl
- 👤 Dinh T. Ngo
- 👤 Paul C. Wang
- 👤 Maria B. L. Hipona
- 👤 Jim Dodrill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 06:02
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/535; G06F7/4824; G06F7/544; G06F7/552; G06F7/5525; G06F2207/00; G06F2207/535; G06F2207/5355; G06F7/483; G06F7/487; G06F7/4873; G06F7/499; G06F7/49942; G06F7/49947; G06F7/49957
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
102 words
Apparatus for calculating a selected value of a quotient or a square root of an operand, comprising: multiplier circuitry having at least first and second inputs receiving first and second numeric signals respectively, said multiplier circuitry including a first portion for producing a product of the first and second numeric signals representing an approximation of the value and a second portion for producing a conversion of said product into a predetermined numeric representation; first feedback circuitry transmitting said conversion to the first input of the multiplier circuitry; and second feedback circuitry transmitting said product to the second input of said multiplier circuitry.
Claim 2
Dependent Claim
102 words
Apparatus for calculating a selected value of a quotient or a square root of an operand, comprising: multiplier circuitry having at least first and second inputs receiving first and second numeric signals respectively, said multiplier circuitry including a first portion for producing a product of the first and second numeric signals representing an approximation of the value and a second portion for producing a conversion of said product into a predetermined numeric representation; first feedback circuitry transmitting said conversion to the first input of the multiplier circuitry; and second feedback circuitry transmitting said product to the second input of said multiplier circuitry.
Claim 3
Dependent Claim
30 words
The apparatus of claim 1 wherein said multiplier circuitry further includes a subtracter connected between said first portion and said second portion for subtracting said product from a constant value.
Claim 4
Dependent Claim
22 words
The apparatus of claim 1 wherein said multiplier circuitry further includes a pipeline register connected between said first portion and said subtracter.
Claim 5
Dependent Claim
17 words
The apparatus of claim 1 wherein said first portion includes circuitry to produce a signed digit product.
Claim 6
Dependent Claim
20 words
The apparatus of claim 1 wherein said second numeric signal can be a signed digit number or a binary number.
Claim 7
Dependent Claim
27 words
The apparatus of claim 1 wherein said second feedback circuitry includes a first memory coupled between said first portion and said first input of said multiplier circuitry.
Claim 8
Dependent Claim
41 words
The apparatus of claim 1 wherein said second feedback circuitry further includes: a first multiplexer coupled between the first memory and a second memory; and a second multiplexer coupled between the second memory and the second input to the multiplier circuitry.
Claim 9
Dependent Claim
42 words
The apparatus of claim 1 wherein the selected value is the quotient and further includes a seed generator coupled to the first and second inputs of said multiplier circuitry for generating an approximation of the reciprocal of a divisor of the operand.
Claim 10
Dependent Claim
37 words
The apparatus of claim 8 wherein the second multiplexer receives signals from the second memory, the seed generator, a first register storing the operand, and a state control circuit and transmits as output said second numeric signal.
Claim 11
Dependent Claim
33 words
The apparatus of claim 8 wherein a third multiplexer receives signals from the seed generator, the second portion of the multiplier circuitry, a second register storing the divisor and the state control circuit.
Claim 12
Dependent Claim
46 words
The apparatus of claim 8 wherein said second portion further includes rounding and compare circuitry coupled between said second portion and said second feedback circuitry for comparing a product of the quotient and the divisor with the operand for determining a direction for rounding the quotient.
Claim 13
Dependent Claim
44 words
The apparatus of claim 1 wherein the selected value is the square root and further includes a seed generator coupled to the first and second inputs of said multiplier circuitry for generating an approximation of a reciprocal of the square root of the operand.
Claim 14
Dependent Claim
45 words
The apparatus of claim 1 wherein said second portion further includes rounding and compare circuitry coupled between said second portion and said second feedback circuitry for comparing a square of the square root with the operand for determining a direction for rounding the square root.
Claim 15
Dependent Claim
15 words
The apparatus of claim 1 wherein said predetermined numeric representation is a binary magnitude representation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-30 | 1993-05-01 | 1993-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-30 | 1997-05-01 | 1997-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-30 | 2001-05-01 | 2001-10-31 | $7700.00 | Window Closed / Lapsed |