Method and apparatus for division using interpolation approximation

Claim 2

A divide apparatus comprising: normalizing means for normalizing a divisor and a dividend; table means for storing a plurality of approximate reciprocal divisors, said table means further storing differences, corresponding to respective ones of said approximate reciprocal divisors, between said respective ones and adjacent others of said approximate reciprocal divisor, and outputting said approximate reciprocal divisor difference by using the high-order bits of the normalized divisor from said normalizing means as an address of said table means; interpolation approximation circuit means for outputting an approximate reciprocal divisor obtained through interpolation approximation in accordance with said approximate reciprocal divisor and difference from said table means and a plurality of bits following said high-order bits of the normalized divisor as the address of said table means; and multiplier means input with said normalized divisor and dividend and the interpolation approximated approximate reciprocal divisor from said interpolation approximation circuit means for outputting a quotient through multiplication.

Claim 3

A divide apparatus according to claim 1, wherein said interpolation approximation circuit means includes: circuit means for proportionally allotting said difference in accordance with a plurality of bits following the high-order bits of said normalized divisor as the address of said table means and for outputting a difference proportionate to the value of said plurality of bits; and addition means for adding said proportional difference to said approximate reciprocal divisor and for outputting an interpolation approximated approximate reciprocal divisor.

Claim 4

A divide apparatus according to claim 2, wherein said circuit means includes means for generating a multiple of said difference represented by the number of said plural bits.

Claim 5

A divide apparatus according to claim 1, wherein said multiplication means has means for inputting the multiplication result output so as to perform successive iterations.

Claim 6

A divide apparatus according to claim 4 further including partial quotient correction means connected to said multiplication means for correcting the partial quotient obtained at each successive iteration by said multiplication means.

Claim 7

A divide apparatus according to claim 1 further including partial quotient correction means connected to said multiplication means for correcting the partial quotient from said multiplication means.

Claim 8

A divide method for use in a data processing system which has a normalization circuit for normalizing an operand, a table unit for storing a plurality of approximate reciprocal divisors M 0 and differences Δ, corresponding to respective ones of said approximate reciprocal divisors, between said respective ones and adjacent others of said approximate reciprocal divisors, an interpolation approximation circuit, a multiplication unit, and a partial quotient correction circuit, comprising the steps of: outputting a normalized divisor D 0 and a normalized dividend N 0 normalized both by said normalization circuit; addressing said table unit by the high-order bits of said normalized divisor D 0 in order to access said approximate reciprocal M 0 and difference Δ; adding a difference proportionate to the value of plural bits following said high-order bits of the normalized divisor as the address of said table unit to said difference Δ in order to obtain an interpolation approximated approximate reciprocal divisor M in said interpolation approximation circuit; multiplying in said multiplication unit said normalized divisor D 0 by said interpolation approximated approximate reciprocal divisor M; performing 1-D 0 ×M in said multiplication unit in order to obtain A by using said D 0 ×M; multiplying in said multiplication unit said normalized dividend N 0 by said interpolation approximated approximate reciprocal divisor M in order to obtain Q 1 +N 1 as a partial quotient Q 1 ; and performing in said multiplication unit successive iterations of A×Q i-1 +N i-1 in order to obtain Q i +N i .

Claim 9

A divide method for use in a data processing system which has a normalization circuit for normalizing an operand, a table unit for storing a plurality of approximate reciprocal divisors M 0 and differences Δ, corresponding to respective ones of said approximate reciprocal divisors, between said respective ones and adjacent others of said approximate reciprocal divisors, an interpolation approximation circuit, a multiplication unit, and a partial quotient correction circuit, comprising the steps of: outputting a normalized divisor D 0 and a normalized dividend N 0 normalized both by said normalization circuit; addressing said table unit by the high-order bits of said normalized divisor D 0 in order to access said approximate reciprocal M 0 and difference Δ; adding a difference proportionate to the value of plural bits following said high-order bits of the normalized divisor as the address of said table unit to said difference Δ in order to obtain an interpolation approximated approximate reciprocal divisor M in said interpolation approximation circuit; multiplying in said multiplication unit said normalized divisor D 0 by said interpolation approximated approximate reciprocal divisor M; performing 1-D 0 ×M in said multiplication unit in order to obtain A by using said D 0 ×M; multiplying in said multiplication unit said normalized dividend N 0 by said interpolation approximated approximate reciprocal divisor M in order to obtain Q 1 +N 1 as a partial quotient Q 1 ; and performing in said multiplication unit successive iterations of A×Q i-1 +N i-1 in order to obtain Q i +N i .

Claim 10

A divide method according to claim 7 further including a step of correcting in said partial quotient correction circuit a partial quotient obtained at each successive iteration.